I'm trying to optimize and understand interrupt latency on the device and am trying to clear a few things up. First, according to this:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16366.html
it seems that interrupt latency can be as low as 12 clock cycles (at least for a base reference design), plus another 17 possible with FPU. As far as I can tell this is implementation dependent.
My measurements seem to indicate the 12+17 cycle latency for this device (~242ns with 120MHz clock). I am using a PWM rising edge to GPIO toggle in the PWM interrupt to roughly measure this latency.
Additionally, the FPU function descriptions in driverlib seem to indicate that interrupt latency can vary using different settings (FPUStackingDisable, FPULazyStackingEnable, FPUStackingEnable, etc...). I am changing these and noticing no difference, however. Also, whenever I set FPUDisable(), I eventually hit a Hwi_excHandler, even though I also tell the compiler to stop using HW FPU instructions (--float_support=none).
My questions:
1) Is the 12+17 number expected for this device?
2) Why am I seeing no difference in interrupt latency when enabling or disabling FPU configurations that are documented as affecting it?
3) Would disabling the FPU entirely drop the 12+17 to just 12, or is that the absolute minimum available?
4) What is the proper procedure for disabling the FPU? It seems the default is Enabled with FPUStacking disabled (at least in my TI RTOS based project)
Thanks!