MSP430F6721: What could go wrong when interfacing with Arm M0 MCUs via UART?

Hi Gary,

Thanks for your reply. The clock is sourced from watch crystal as reference:

	//Turn on XT1 watch crystal, wait til XT1 stablize
	UCSCTL6 &= ~(XT1OFF);                  							// XT1 On
	UCSCTL6 |= XCAP_3;                     							// Internal load cap
	UCSCTL3 |= SELREF__REFOCLK;             						// Set DCO FLL reference = REFO
	UCSCTL4 = SELA__XT1CLK | SELS__DCOCLKDIV | SELM__DCOCLK;      	// Set ACLK = XT1, SMCLK = DCOCLKDIV, MCLK = DCOCLK
	__bis_SR_register(SCG0);               							// Disable the FLL control loop
	UCSCTL0 = 0x0000;                      							// Set lowest possible DCOx, MODx
	UCSCTL1 = DCORSEL_5;                   							// Select DCO range 16MHz operation
	UCSCTL2 = FLLD_2 | 121;                							// fDCOCLK = 4 * (121 + 1) * 32768 = 15,990,784Hz, fSMCLK = 4MHz
	__bic_SR_register(SCG0);               							// Enable the FLL control loop
	do {
		UCSCTL7 &= ~(XT2OFFG | XT1LFOFFG | DCOFFG);					// Clear XT2,XT1,DCO fault flags
	    SFRIFG1 &= ~OFIFG;                 							// Clear fault flags
	} while (SFRIFG1 & OFIFG);  

The following is code to initialize UART:

	P1SEL |= BIT2 | BIT3;                   // Set P1.2, P1.3 to non-IO
	P1DIR |= BIT2 | BIT3;                   // Enable UCA0RXD, UCA0TXD
	UCA0CTLW0 |= UCSWRST;                   // **Put state machine in reset**
	UCA0CTLW0 |= UCSSEL_1;                  // CLK = ACLK
	UCA0BRW_L = 0x03;                       // 32kHz/9600=3.41 (see User's Guide)
	UCA0BRW_H = 0x00;                       //
	UCA0MCTLW = 0x5300;                     // Modulation UCBRSx=0x53, UCBRFx=0
	UCA0CTLW0 &= ~UCSWRST;                  // **Initialize USCI state machine**
	UCA0IE |= UCRXIE;                    	

Thanks again,

Could be  a RTS and CTS  deadlock . 

Hi Peter,

Could you elaborate this a little more? I assume such deadlock involves both A & B, therefore power cycle B or disconnect/reconnect B to A would break such deadlock. 

This deadlock is when both sides are in the DO NOT SEND DATA state.

A logic analyzer like Salae is helpful here