MSP430FR5969: LPM after employing DMA

Ferran,

I put together a code example that accomplishes exactly what you described in your post. I initialize ACLK to run on the low frequency crystal and then configure the ADC capture to trigger the DMA transfer all while not waking up the device or entering into an interrupt. You can find a current consumption screenshot and the code pasted below. From what I can tell, once the boot code executes and we start the ADC samples the device from there on stays in LPM3 current consumption levels (~1uA) except when sampling the ADC and using the DMA for the data transfer (shown as spikes in the current profile).

#include <msp430.h>
#include <stdint.h>

int main(void)
{
  WDTCTL = WDTPW | WDTHOLD;                 // Stop WDT

  // Configure GPIOs to it's lowest power state
  P1OUT = 0;                                // All P1.x reset
  P1DIR = 0xFF;                             // All P1.x outputs
  P2OUT = 0;                                // All P2.x reset
  P2DIR = 0xFF;                             // All P2.x outputs
  P3OUT = BIT0;                                // All P3.x reset
  P3DIR = 0xFF;                             // All P3.x outputs
  P4OUT = 0;                                // All P4.x reset
  P4DIR = 0xFF;                             // All P4.x outputs
  PJOUT = 0;                                // All PJ.x reset
  PJDIR = 0xFFFF;                           // All PJ.x outputs

  // Set up XT1
  PJSEL0 = BIT4 | BIT5;                     // For XT1

  P1SEL0 |= BIT2;                           // configure P1.2/A2 for ADC function
  P1SEL1 |= BIT2;                           //

  // Disable the GPIO power-on default high-impedance mode to activate
  // previously configured port settings
  PM5CTL0 &= ~LOCKLPM5;

  // Clock System Setup
  CSCTL0_H = CSKEY >> 8;                    // Unlock CS registers
  CSCTL1 = DCOFSEL_0;                       // Set DCO to 1MHz
  CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK;
  CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1;     // Set all dividers
  CSCTL4 &= ~LFXTOFF;

  do
  {
    CSCTL5 &= ~LFXTOFFG;                    // Clear XT1 fault flag
    SFRIFG1 &= ~OFIFG;
  } while (SFRIFG1 & OFIFG);                // Test oscillator fault flag

  // Configure DMA channel 0
  __data20_write_long((uintptr_t) &DMA0SA,(uintptr_t) &ADC12MEM0 );   //Write from ADC12MEM0
                                            // Source block address
  __data20_write_long((uintptr_t) &DMA0DA,(uintptr_t) 0x1C40 );      //Destination address
                                            // Destination single address
  DMACTL0 |= DMA0TSEL_26;                   // DMA triggered by ADC12 End of Conversion
  DMA0SZ = 1;                               // Transfer one byte/word
  DMA0CTL = DMADT_4 | DMAIE; // Rpt single transfer, enable interrupt if GIE is set
  DMA0CTL |= DMAEN;                         // Enable DMA0

  ADC12CTL0 = ADC12SHT0_0 | ADC12ON;        // Sampling time, S&H=4, ADC12 on
  // Use TA0.1 to trigger, and repeated-single-channel
  ADC12CTL1 = ADC12SHP | ADC12SHS_1 | ADC12CONSEQ_2;
  // A2 ADC input select; Vref+ = VREF
  ADC12MCTL0 = ADC12INCH_2 | ADC12VRSEL_1 | ADC12EOS;

  //ADC12IER0 |= ADC12IE0;                    // Enable ADC interrupt
  ADC12CTL0 |= ADC12ENC | ADC12SC;          // Start sampling/conversion

  // Configure Timer0_A3 to periodically trigger the ADC12
  TA0CCR0 = 2048-1;                         // PWM Period
  TA0CCTL1 = OUTMOD_3;                      // TACCR1 set/reset
  TA0CCR1 = 2047;                           // TACCR1 PWM Duty Cycle
  TA0CTL = TASSEL__ACLK | MC__UP;           // ACLK, up mode
//  __bis_SR_register(LPM3_bits | GIE);       // Enter LPM3, enable interrupts
  __bis_SR_register(LPM3_bits);             //Stay in LPM forever

  return 0;
}

Best regards,

Matt

Ferran,

As long as the peripherals are configured correctly, and the capture and memory write sequence only starts once the configuring is finished, it should not matter which peripheral is initialized first.

Also the "data write 16" should be fine since you are not writing to the 20 bit address space.

I started from separate ADC and DMA code examples and merged them from there to get the example I shared above. In your case, if the example I shared above is working as expected on your hardware then you should be able to work off of that to continue developing your project.

I am not certain what the differences are between our projects but your best bet is to map out all of the register initializations right before you hit the "__bis_SR_register(LPM3_bits)" line for both projects and see what the differences are from there.

Best regards,

Matt