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Original question:

MSP430I2030: About the linearity error of SD24

MSP430I2030: About difference in linearity error of SD24 due to Vic

user6002548
Prodigy 80 points
Part Number: MSP430I2030

Dear all,

 

when the linearity error was measured by setting gain to 1 and changing Vic to 0 V, 0.1 V, and 1.0 V,

the shape of the graph was different when Vic was 0.1 V.(Please refer to the attached graph.)

INL.pdf

Why is this going to happen?

 

The test procedure is as follows.

(1)Place the PCB in a thermostat bath and set the ambient temperature to 25 °C.

(2)After the temperature stabilizes, turn on the 3.3V power and leave it for 30 minutes.

(3)Set SD24 to 24 bit and the gains of AI0-3 to 1x.

(4)Input a voltage of 0% when the ADC input full scale is (± Vref / gain × 0.8).

(5)Switch the multiplexer to AI0, AI1, AI2, AI3 and measure the input voltage of each channel.

　Output ADC values ​​of 1000 samples of AI0, AI1, AI2 and AI3 by UART communication and record them with time stamped log.

(6)The input voltage is changed in the range of 0% to 100% and 0% to -100% in 1% steps, and (5) is performed at each input voltage.

(7)Change Vic and do the same test.

 

*I used internal voltage(1.158V)

*Only one PCB board can be evaluated.

* I tested on all 4ch and the results were the same.

* 1000 samples are averaged after send via UART.

*The ideal straight line is calculated based on the ADC value when ± 95% (± 1.158 * 0.8 * 0.95 V) of the input ADC value is input.

 

We are asked by our customer to explain this.

Please tell me why you can think of it.

 

Best regards,

Megumi Nishi

  • 0
    TI__Mastermind 49692 points

    Hello,

    user6002548 said:
    the shape of the graph was different when Vic was 0.1 V.

    What does "Vic" mean? Is this a common-mode voltage input or differential voltage from + to - inputs?

    user6002548 said:
    (4)Input a voltage of 0% when the ADC input full scale is (± Vref / gain × 0.8).

    So you're starting at Vic = 0V?

    user6002548 said:
    (5)Switch the multiplexer to AI0, AI1, AI2, AI3 and measure the input voltage of each channel.

    You don't need to reconfigure the ADC channels every time you change the input voltage. Once they're configured, they'll continue to sample at the specified sampling frequency and resolution. I would change this.

    user6002548 said:
    (6)The input voltage is changed in the range of 0% to 100% and 0% to -100% in 1% steps, and (5) is performed at each input voltage.

    Why don't you start from -100% and go to +100% to keep the input monotonic and continuous rather than starting in the middle?

    Are you using the SD24INTDLY bit? This bit selects the delay for the first interrupt after conversion start (either one or four sample delay).

    Regarding your analog input setup, please keep in mind what is described by Section 13.2.6.2 in the User's Guide.

    During conversion, any modification of the SD24INCTLx register becomes effective with the next decimation step of the digital filter. After these bits are modified, the next three conversions may be invalid due to the settling time of the digital filter. This can be handled automatically with the SD24INTDLY bit. When SD24INTDLY = 0b, conversion interrupt requests do not begin until the fourth conversion after a start condition. An external RC anti-aliasing filter is recommended for the SD24 to prevent aliasing of the input signal. The cutoff frequency should be less than 10 kHz for a 1-MHz modulator clock and OSR = 256. The cutoff frequency may be set to a lower frequency for applications that have lower bandwidth requirements.

    In 'Vic.xlsx', how are you calculating the LSB? Are the values shown (e.g. -600) in decimal format?

    What format are you using: offset binary, twos complement?

    What OSR are you using?

    Regards,

    James

  • 0 in reply to James Evans
    Prodigy 80 points

    Dear James,

    thank you for your message.
    And I'm sorry for my late reply.

    As a result of checking this matter by myself, I found that there is a problem in the measurement environment. So close it.

    Best regard,
    Megumi

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