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MSP430F6779: I have a question about MSP430 RTC Reading.

Expert 2780 points
Part Number: MSP430F6779

I have a question about MSP430 RTC_C.

When we read the RTC_C register, we may use an interrupt or decide on a majority decision.

When making a majority vote, read the register value.
At this time, is it not a problem to recognize that RTCRDY is set?

When should this RTCRDY be read?
Before reading RTC's register (YEAR / MONTH ...), after reading register, before or after reading it?

Regards,
Da

  • Hi,

    in the MSP430F6xx User's Guide, you can find further details on the RTCRDY functionality, but for your convenience, please find here the main section copied here

    "In calendar mode, the real-time clock registers are updated once per second. To prevent reading any realtime
    clock register at the time of an update, which could result in an invalid time being read, a keepout
    window is provided. The keepout window is centered approximately -128/32768 s around the update
    transition. The read-only RTCRDY bit is reset during the keepout window period and set outside the
    keepout the window period. Any read of the clock registers while RTCRDY is reset is considered to be
    potentially invalid, and the time read should be ignored.
    An easy way to safely read the real-time clock registers is to use the RTCRDYIFG interrupt flag. Setting
    RTCRDYIE enables the RTCRDYIFG interrupt. Once enabled, an interrupt is generated based on the
    rising edge of the RTCRDY bit, causing the RTCRDYIFG to be set. At this point, the application has
    nearly a complete second to safely read any or all of the real-time clock registers. This synchronization
    process prevents reading the time value during transition. The RTCRDYIFG flag is reset automatically
    when the interrupt is serviced, or can be reset with software."

    For further details, please see the User's Guide Best regards

    Peter

  • Hi,

    under the assumption your questions have been answered sufficiently, I am closing the thread. In case you should have additional questions, please let us know.

    Best regards

    Peter

  • Hello,

    as you rejected the answer, it seems your problem is not solved. Sorry for that. So could you please give us an update on the status of your problem with an indication what aspect needs to be addressed? Many thanks in advance.

    Best regards

    Peter

  • Hello,

    we think your question has been addressed by the copied section of the UG, as it exactly addressing the functionality of RTCRDY. Please see once again

    "In calendar mode, the real-time clock registers are updated once per second. To prevent reading any realtime
    clock register at the time of an update, which could result in an invalid time being read, a keepout
    window is provided. The keepout window is centered approximately -128/32768 s around the update
    transition. The read-only RTCRDY bit is reset during the keepout window period and set outside the
    keepout the window period. Any read of the clock registers while RTCRDY is reset is considered to be
    potentially invalid, and the time read should be ignored.
    An easy way to safely read the real-time clock registers is to use the RTCRDYIFG interrupt flag. Setting
    RTCRDYIE enables the RTCRDYIFG interrupt. Once enabled, an interrupt is generated based on the
    rising edge of the RTCRDY bit, causing the RTCRDYIFG to be set. At this point, the application has
    nearly a complete second to safely read any or all of the real-time clock registers. This synchronization
    process prevents reading the time value during transition. The RTCRDYIFG flag is reset automatically
    when the interrupt is serviced, or can be reset with software."

    For further details, please see the User's Guide

    If some aspects is not addressed by our documentation, please give us a more detailed explanation on the missing details. Until then we're closing this thread.

    Best regards

    Peter

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