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Part Number: TIDM-FRAM-EEPROM
Hi community member,
I have a question about the SPI clock of TIDM-FRAM-EEPROM.
<Question>1. Do you think it is possible to design for faster SPI clock (eg 10 MSPS)?My customer wants to communicate at speeds faster than 1MSPS.The Design Guide says:
This design is also designed to support EEPROM emulation with SPI and supports slave clock polarity high with rising edge as the trigger. This example is capable of supporting SPI clocks up to 1 Mbps using the direct memory access (DMA). All MSP430FR5x and MSP430FR6x devices have onboard DMA.
2. If TIDM-FRAM-EEPROM design is not capable of SPI Clock of 10 MSPS, LPM is considered to be one of the factors.Do you think that the CPU can support 10MSPS if it is SPI communication in always active mode?I think it can omit the wake-up time from LPM and interrupt latency.
I am looking into this and will provide an update tomorrow.
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In reply to Mitch Ridgeway:
We can provide the SPI module with a maximum clock frequency of 16MHz without breaking the device:
However, we need to consider the SPI timing requirements of the 2 devices to determine the max SPI clock frequency where we can get valid data. There is an excellent post that outlines these timing requirements and how to calculate them using the device datasheet. This post can be referenced in the link below:
I went ahead and calculated the maximum SPI frequency we can get from the devices used in the TI design you reference, and it looks like we can get a maximum frequency of 7MSPS. Anything higher than this will put us at risk for getting invalid data.
In short - I think it's possible to design for SPI speeds above 1MHz, but not for 10MHz.
Please check out the link I provided - it is a great resource that goes in depth about calculating maximum reliable SPI baud rates.
Sorry for the late reply.
I proposed to my customer along with the link calculation method.
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