This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430FR2110: About faster startup time

Part Number: MSP430FR2110
Other Parts Discussed in Thread: MSP430FR2311, MSP-TS430PW20

Hello everyone,

Using MSP430FR2110
I want to make the time from power on to P1.0 = "Hi" 40ms or less. MCLK must be 16MHz.
The current software takes 138ms processing time.
About DCO Software Trim
I referred MSP430 Hardware Tools User's Guide .pdf.
47ms time is spent on Software_Trim () processing.
- What are your concerns if you execute processing without waiting for FLL Lock?
- Please give me advice on how to increase the startup time.

int main(void)
{
    /* Port-1 Initialization */
 P1DIR  = 0x31;
 P1REN  = 0x08;
 P1OUT  = 0x00;
 P1SEL0 = 0x02;
 P1SEL1 = 0xc2;
 P1IES  = 0x08; /* P1.3 Interrupt Low Edge */
 P1IE   = 0x08; /* P1.3 Interrupt Enable */

 WDTCTL = WDTPW + WDTHOLD; /* Stop watchdog timer */

    PM5CTL0 &= ~LOCKLPM5;       // Disable the GPIO power-on default high-impedance mode
                                // to activate previously configured port settings

 FRCTL0 = FRCTLPW | NWAITS_1;   /* Set FRAM wait state to 1 */
 
 Clock_Setting();

 __bis_SR_register( GIE );  /* interrupts enabled */

 P1OUT |= 0x01;

 while( 1 ){}
}

void Clock_Setting()
{
    __bis_SR_register(SCG0);                // disable FLL
    CSCTL3 |= SELREF__REFOCLK;              // Set REFO as FLL reference source

    CSCTL1 = DCOFTRIMEN_1 | DCOFTRIM0 | DCOFTRIM1 | DCORSEL_5; // DCOFTRIM=3, DCO Range = 16MHz
    CSCTL2 = FLLD_0 + 488;                  // DCODIV = 16.023552MHz

    __delay_cycles(3);
    __bic_SR_register(SCG0);                // enable FLL

    Software_Trim();                        // Software Trim to get the best DCOFTRIM value

    CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                            // default DCODIV as MCLK and SMCLK source

}

void Software_Trim()
{
    unsigned int oldDcoTap = 0xffff;
    unsigned int newDcoTap = 0xffff;
    unsigned int newDcoDelta = 0xffff;
    unsigned int bestDcoDelta = 0xffff;
    unsigned int csCtl0Copy = 0;
    unsigned int csCtl1Copy = 0;
    unsigned int csCtl0Read = 0;
    unsigned int csCtl1Read = 0;
    unsigned int dcoFreqTrim = 3;
    unsigned char endLoop = 0;

    do
    {
        CSCTL0 = 0x100;                         // DCO Tap = 256
        do
        {
            CSCTL7 &= ~DCOFFG;                  // Clear DCO fault flag
        }while (CSCTL7 & DCOFFG);               // Test DCO fault flag

        if(mclk == MCLK16MHz ) __delay_cycles((unsigned int)3000 * 16);// Wait FLL lock status (FLLUNLOCK) to be stable
                                                           // Suggest to wait 24 cycles of divided FLL reference clock

        while((CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)) && ((CSCTL7 & DCOFFG) == 0));

        csCtl0Read = CSCTL0;                   // Read CSCTL0
        csCtl1Read = CSCTL1;                   // Read CSCTL1

        oldDcoTap = newDcoTap;                 // Record DCOTAP value of last time
        newDcoTap = csCtl0Read & 0x01ff;       // Get DCOTAP value of this time
        dcoFreqTrim = (csCtl1Read & 0x0070)>>4;// Get DCOFTRIM value

        if(newDcoTap < 256)                    // DCOTAP < 256
        {
            newDcoDelta = 256 - newDcoTap;     // Delta value between DCPTAP and 256
            if((oldDcoTap != 0xffff) && (oldDcoTap >= 256)) // DCOTAP cross 256
                endLoop = 1;                   // Stop while loop
            else
            {
                dcoFreqTrim--;
                CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4);
            }
        }
        else                                   // DCOTAP >= 256
        {
            newDcoDelta = newDcoTap - 256;     // Delta value between DCPTAP and 256
            if(oldDcoTap < 256)                // DCOTAP cross 256
                endLoop = 1;                   // Stop while loop
            else
            {
                dcoFreqTrim++;
                CSCTL1 = (csCtl1Read & (~DCOFTRIM)) | (dcoFreqTrim<<4);
            }
        }

        if(newDcoDelta < bestDcoDelta)         // Record DCOTAP closest to 256
        {
            csCtl0Copy = csCtl0Read;
            csCtl1Copy = csCtl1Read;
            bestDcoDelta = newDcoDelta;
        }

    }while(endLoop == 0);                      // Poll until endLoop == 1

    CSCTL0 = csCtl0Copy;                       // Reload locked DCOTAP
    CSCTL1 = csCtl1Copy;                       // Reload locked DCOFTRIM
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
}

hank you in advance.
Best regards,

k.saito

  • Hi,

    If there is no wait for FLL Lock after FLL module configuration, there may be a risk of crashing.

    Why do you need a startup time of less than 40ms? Can you provide details about your application?

    Some suggestions that may reduce startup time:

    • Using assembly language, this can skip the execution of the boot.c file, and the efficiency will be higher.
    • If you want to execute some necessary code after fast startup, Could you execute FLL initialization after executing these code?
    • If the MSP430 is startup from a low-power mode, it may save time for FLL initialization, such as LPM3.5/LPM4.5 mode, but the FLL initialization is still required for the first power-on.

    Best Regards

    Johnson

  • Thank you for your reply.
    >If there is no wait for FLL Lock after FLL module configuration, there may be a risk of crashing.
    I understand.
    > Why do you need a startup time of less than 40ms? Can you provide details about your application?
    MSP430 is used as a slave system. The master side is an existing system and outputs a signal within 40ms after starting the slave. For this reason, the slave must start within 40 ms and be in a state where it can receive the master signal.
    To check the startup time, we measured the time from when the power was turned on until P1.0 became Hi.
    > •Using assembly language, this can skip the execution of the boot.c file, and the efficiency will be higher.
    I do n’t know what to do, Can you provide sample source?
    > •If you want to execute some necessary code after fast startup, Could you execute FLL initialization after executing these code?
    The master outputs an interrupt with a period of 212KHz 40ms after starting the slave.
    For this reason, there is no time to initialize the FLL after startup.
     if(mclk == MCLK16MHz ) __delay_cycles((unsigned int)3000 * 16);    // Wait FLL lock status (FLLUNLOCK) to be stable
                                                                                                                    // Suggest to wait 24 cycles of divided FLL reference clock
    Can I shorten the time waiting for 3000ms in the sample?
    For example 1000ms.
  • I made the following mistake:
    Cycle was mistaken for ms.

    if(mclk == MCLK16MHz ) __delay_cycles((unsigned int)3000 * 16);    // Wait FLL lock status (FLLUNLOCK) to be stable
                                                                                                                    // Suggest to wait 24 cycles of divided FLL reference clock

    Can I shorten the time waiting for 3000cycle in the sample?
    For example 1000cycle.
  • Hi,

    1. For assembly language, we provide some code example for customer, you can refer to this link:

       http://dev.ti.com/tirex/explore/node?node=AMxpbVoxQwHnVaf2jw1Mrg__IOGqZri__LATEST

       However, I tested the method of using assembly language on FR2311, but the results are not good, and the time is basically not shortened.

    2. The way you describe 3000 cycle to 1000 cycle, the result does not necessarily shorten the startup time, because the startup time is mainly consumed in wait for the FLL lock, not in this place, thus this action may cause the opposite result, resulting in longer startup time. I tested on FR2311 that if I change 3000 cycle to 1000 cycle, the startup time will be longer.

    3. Why do you need MCLK to be 16MHz, for the communication or other purposes? the default frequency can not be completed?

    4. In response to this situation, the following analysis and recommendations:

    The main consumption of startup time is from low frequency multiplication to high frequency, such as REFCLK (32768Hz) to MCLK (16MHz), so waiting time is required to this process.


    Are you willing to replace similar MCU products? For MSP430FR2311 or other similar products, the internal clock module is HFXT (FR2110 is LFXT), so it can be directly connected to the external 16MHz crystal oscillator. This method can greatly shorten the startup time. In our Datasheet, the startup time is about 1ms, as shown below:

    Or other series MSP430 MCU, such as the MSP430G2xx F2xx, which can be directly set to 16MHz by setting digital DCO clock. It may save a lot of startup time because it don't need FLL module. 

    Best Regards

    Johnson

  • Thank you for the advice.
    > 1. For assembly language, we provide some code example for customer, you can refer to this link:
    OK. I will refer to it.
    > 2. The way you describe 3000 cycle to 1000 cycle, the result does not necessarily shorten the startup time, because the startup time is
    > mainly  consumed in wait for the FLL lock, not in this place, thus this action may cause the opposite result, resulting in longer startup time. I
    > tested on > FR2311 that if I change 3000 cycle to 1000 cycle, the startup time will be longer.
    I understand.
    What is the minimum number of cycles to wait for?
    Is it still 3000cycle?
    > 3. Why do you need MCLK to be 16MHz, for the communication or other purposes? the default frequency can not be completed?
    Since the master side outputs an interrupt signal to the slave at an interval of 212KHz, it is necessary to complete the interrupt processing within 4.7us. For this reason, it will not be in time without processing at 16 MHz.
    > 4. In response to this situation, the following analysis and recommendations:
    Thank you for introducing MSP430FR2311.
    I will check the details with the constraints of the mounting area.
  • thank you for your answer.

    Please tell us about the following crashes.

    >If there is no wait for FLL Lock after FLL module configuration, there may be a risk of crashing.

    Which is a hard crash or a soft crash?
    When not waiting for FLL lock,
    I think that the program counter advances with an indefinite clock in terms of software.
    Please tell me how it crashes.

  • Hi,

    There are maybe some unpredictable problem if other codes are run without waiting for stability after initializing the FLL, and there have been crashes before.

    For your request of start-up quickly(less 40ms), we found a solution. some details as follow:

    You can close FLL module, just use DCO module to create a 16MHz clock.

    There may be errors in frequency due to the FLL module being disabled. However, each chip have calibration value for the DCO clock in TLV structure. This value can be read to set the DCO clock to get an accurate 16MHz.


    This solution is only for operating the registers, there is no need to wait for the cloak to stabilize, so the startup time is faster and should meet your requirements.

    Attach my test code:

    #include <msp430.h>
    #define DCO_CALIBRATION_ADDR 0x1A22
    
    int main(void)
    {
        WDTCTL = WDTPW | WDTHOLD;                          // Stop watchdog timer
    
        // Configure one FRAM waitstate as required by the device datasheet for MCLK
        // operation beyond 8MHz _before_ configuring the clock system.
        FRCTL0 = FRCTLPW | NWAITS_1;
    
        P2DIR |= BIT6;
        P2OUT |= BIT6;
    
        __delay_cycles(8000);                            // Delay
    
        P2OUT &= ~BIT6;
    
        __bis_SR_register(SCG0);                         // Disable FLL
        CSCTL0 = 0;                                      // Clear DCO and MOD registers
        CSCTL0 |= *(unsigned int *)DCO_CALIBRATION_ADDR; // Set DCO from calibration of TLV
        CSCTL1 &= ~DCORSEL_7;                            // Clear DCORSEL bits first
        CSCTL1 |= DCORSEL_5;                             // Set DCO = 16MHz
        CSCTL2 &= ~FLLD_7;                               // Clear FLLD registers
        CSCTL2 |= FLLD_0;                                // Set FLLD = 0, Not divide the DCOCLK clock
        __delay_cycles(3);
    
        CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;       // Set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                         // default DCOCLKDIV as MCLK and SMCLK source
    
        CSCTL5 |= DIVS_2 + DIVM_0;                       // MCLK = DCOCLK = 16MHz
                                                         // SMCLK = MCLK/4 = 4MHz
        P1DIR |= BIT0 | BIT1;                            // Set ACLK SMCLK as output
        P1SEL1 |= BIT0 | BIT1;                           // Set ACLK and SMCLK pin as second function
    
        P2OUT |= BIT6;
        PM5CTL0 &= ~LOCKLPM5;                            // Disable the GPIO power-on default high-impedance mode
                                                         // to activate previously configured port settings
    
        while(1)
        {
            __delay_cycles(8000);
        }
    }
    

    Best Regards

    Johnson

  • Thank you for your suggestion.
    We program and confirm by referring to the sample code.
    Please tell us the following:
    Q1. In the case of DCO Direct, is there a risk of crash even if the frequency is switched?
    Q2. Please let me know the calibration value at 12MHz setting. (Can the calibration value be switched?)
    Q3.Please tell me the frequency accuracy and temperature characteristics of DCO.
  • Hi, 

    For Q1. In the case of DCO Direct, is there a risk of crash even if the frequency is switched?

    This usage way of  DCO is normal mode and has a corresponding chapter description in the user's guide, so there is no risk of crash.

    For Q2. Please let me know the calibration value at 12MHz setting. (Can the calibration value be switched?)

    We only have a 16MHz calibration value in the TLV structure, you need to calibrate yourself if you would like to set system clock to 12MHz. This calibration value can be modified, but it will cover the original 16MHz calibration value, it is recommended to store the calibration data(12MHz) into FRAM.

    For Q3. Please tell me the frequency accuracy and temperature characteristics of DCO.

    I'm sorry to that we don't have those test data for your question, why do you need a high precision clock?

    Best Regards

    Johnson

  • Thank you for answering.

    >For Q1. In the case of DCO Direct, is there a risk of crash even if the frequency is switched?

    This usage way of  DCO is normal mode and has a corresponding chapter description in the user's guide, so there is no risk of crash.

    I understand.

    >For Q2. Please let me know the calibration value at 12MHz setting. (Can the calibration value be switched?)

    We only have a 16MHz calibration value in the TLV structure, you need to calibrate yourself if you would like to set system clock to 12MHz. This calibration value can be modified, but it will cover the original 16MHz calibration value, it is recommended to store the calibration data(12MHz) into FRAM.

    Does it mean that the DCO tap value is calibrated for each device and stored in FRAM?
    What are the risks when DCORSEL is set to 12MHz using the 16MHz calibration value in the TLV structure?
    Please tell me the calibration procedure.

    >For Q3. Please tell me the frequency accuracy and temperature characteristics of DCO.

    I'm sorry to that we don't have those test data for your question, why do you need a high precision clock?

    As the required specification, the interrupt processing must be completed within 4.7us, so we wanted to confirm the temperature characteristics of the DCO as evidence.
    Since execution time is critical, accuracy of 5% or less is required.
    I understand that there is no data. Please tell me the design value.

    Best Regards

    k.saito

  • Hi K.saito,

    There have some test data maybe useful for you in datasheet :

    And those test condition is enable FLL, and in order to meet your requirement : both start-up quickly and High precision clock, You can use the DCO calibration value and enable the FLL at the same time, which will Drastically reduce the FLL lock time.

    Attach some code for this way:

    #include <msp430.h>
    #define DCO_CALIBRATION_ADDR 0x1A22
    
    int main(void)
    {
        WDTCTL = WDTPW | WDTHOLD;                          // Stop watchdog timer
    
        // Configure one FRAM waitstate as required by the device datasheet for MCLK
        // operation beyond 8MHz _before_ configuring the clock system.
        FRCTL0 = FRCTLPW | NWAITS_1;
    
        P2DIR |= BIT6;
        P2OUT |= BIT6;
    
        __delay_cycles(8000);                            // Delay
    
        P2OUT &= ~BIT6;
    
        __bis_SR_register(SCG0);                           // disable FLL
        CSCTL3 |= SELREF__REFOCLK;                         // Set REFO as FLL reference source
        CSCTL0 = 0;                                        // Clear DCO and MOD registers
        CSCTL0 |= *(unsigned int *)DCO_CALIBRATION_ADDR;   // clear DCO and MOD registers
        CSCTL1 &= ~(DCORSEL_7);                            // Clear DCO frequency select bits first
        CSCTL1 |= DCORSEL_5;                               // Set DCO = 16MHz
        CSCTL2 = FLLD_0 + 487;                             // DCOCLKDIV = 16MHz
        __delay_cycles(3);
        __bic_SR_register(SCG0);                           // enable FLL
        while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));         // FLL locked
    
    
        CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;       // Set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                         // default DCOCLKDIV as MCLK and SMCLK source
    
        CSCTL5 |= DIVS_2 + DIVM_0;                       // MCLK = DCOCLK = 16MHz
                                                         // SMCLK = MCLK/4 = 4MHz
        P1DIR |= BIT0 | BIT1;                            // Set ACLK SMCLK as output
        P1SEL1 |= BIT0 | BIT1;                           // Set ACLK and SMCLK pin as second function
    
        P2OUT |= BIT6;
        PM5CTL0 &= ~LOCKLPM5;                            // Disable the GPIO power-on default high-impedance mode
                                                         // to activate previously configured port settings
    
        while(1)
        {
            __delay_cycles(8000);
        }
    }
    

    Best Regards

    Johnson

  • Hi

    Thank you for a great suggestion.
    We evaluated the following two cases based on advice.
    In both cases, it was about 50us until P1.0 became Hi.
    However, the frequency of MCLK was confirmed at the timing when P1.0 becomes Hi, and in both cases it was 16.6MHz.
    I have a question about the above.
    Q1.Why is there no difference in MCLK frequency between case2 and case1?
    Q2.Is there a risk when MCLK goes over 16M?

    -------------case1-------------
    #include <msp430.h>
    #define DCO_CALIBRATION_ADDR 0x1A22

    int main(void)
    {
        WDTCTL = WDTPW | WDTHOLD;                          // Stop watchdog timer

        // Configure one FRAM waitstate as required by the device datasheet for MCLK
        // operation beyond 8MHz _before_ configuring the clock system.
        FRCTL0 = FRCTLPW | NWAITS_1;

     P1DIR  = 0x01;
     P1OUT  = 0x00;
     P2DIR  = 0x40;
     P2OUT  = 0x40;//P2.6 MCLK OUT
     P2SEL0 = 0x40;//P2.6 MCLK OUT

        __bis_SR_register(SCG0);                         // Disable FLL
        CSCTL0 = 0;                                      // Clear DCO and MOD registers
        CSCTL0 |= *(unsigned int *)DCO_CALIBRATION_ADDR; // Set DCO from calibration of TLV
        CSCTL1 &= ~DCORSEL_7;                            // Clear DCORSEL bits first

        CSCTL1 |= DCORSEL_5;                             // Set DCO = 16MHz
        CSCTL2 &= ~FLLD_7;                               // Clear FLLD registers
        CSCTL2 |= FLLD_0;                                // Set FLLD = 0, Not divide the DCOCLK clock
        __delay_cycles(3);

        CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;       // Set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                         // default DCOCLKDIV as MCLK and SMCLK source

        CSCTL5 |= DIVS_2 + DIVM_0;                       // MCLK = DCOCLK = 16MHz
                                                         // SMCLK = MCLK/4 = 4MHz

        PM5CTL0 &= ~LOCKLPM5;                            // Disable the GPIO power-on default high-impedance mode
                                                         // to activate previously configured port settings
        P1OUT |= 0x01;

        while(1)
        {
            __delay_cycles(8000);
        }
    }

    -------------case2-------------
    #include <msp430.h>
    #define DCO_CALIBRATION_ADDR 0x1A22

    int main(void)
    {
        WDTCTL = WDTPW | WDTHOLD;                          // Stop watchdog timer

        // Configure one FRAM waitstate as required by the device datasheet for MCLK
        // operation beyond 8MHz _before_ configuring the clock system.
        FRCTL0 = FRCTLPW | NWAITS_1;

        P1DIR  = 0x01;
     P1OUT  = 0x00;
     P2DIR  = 0x40;
     P2OUT  = 0x40;//P2.6 MCLK OUT
     P2SEL0 = 0x40;//P2.6 MCLK OUT

        __bis_SR_register(SCG0);                           // disable FLL
        CSCTL3 |= SELREF__REFOCLK;                         // Set REFO as FLL reference source
        CSCTL0 = 0;                                        // Clear DCO and MOD registers
        CSCTL0 |= *(unsigned int *)DCO_CALIBRATION_ADDR;   // clear DCO and MOD registers
        CSCTL1 &= ~(DCORSEL_7);                            // Clear DCO frequency select bits first
        CSCTL1 |= DCORSEL_5;                               // Set DCO = 16MHz
        CSCTL2 = FLLD_0 + 487;                             // DCOCLKDIV = 16MHz
        __delay_cycles(3);
        __bic_SR_register(SCG0);                           // enable FLL
        while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));         // FLL locked


        CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;       // Set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                         // default DCOCLKDIV as MCLK and SMCLK source

        CSCTL5 |= DIVS_2 + DIVM_0;                       // MCLK = DCOCLK = 16MHz
                                                         // SMCLK = MCLK/4 = 4MHz

        PM5CTL0 &= ~LOCKLPM5;                            // Disable the GPIO power-on default high-impedance mode
                                                         // to activate previously configured port settings
        P1OUT |= 0x01;

        while(1)
        {
            __delay_cycles(8000);
        }
    }

  • Hi K.saito,

    This looks like an oscilloscope's measurement error. Our calibration value is 16MHz. Could you try to change the oscilloscope's SACLE value to re-measure it? The waveform of the MCLK clock is not perfect, thus this frequency measurement errors maybe occur.

    Attach the test results I used in your program in FR2311 MCU:

    Case 1 :

    Case 2 :

    Best Regards

    Johnson

  • Hi

    Thank you for the advice.
    I changed the scale of the oscilloscope and took it again.
    Both DCO output and FLL Lock output had a frequency of 16.6MHz.
    I logically think that the FLL Lock output is closer to 16.0MHz.
    Why is the FLL Lock output not 16.0MHz?
    Is this a device specific issue?
    case1:DCO only output
    case2: DCO&FLL Lock output
  • Hi K.saito,

    What is your test environment? The calibration value is obtained in a 30°C environment. You can refer to the information in the picture:

    Have you tried changing a FR2110 chip for testing?

    I used the FR2110 chip for testing. The result shows that the MCLK frequency of both programs(Case 1 and Case 2) is 16MHz.

    Best Regards

    Johnson

  • Hi

    I use the MSP-TS430PW20 evaluation board and MSP-FET430UIF as a debugger.
    The ambient temperature is 25 ° C at room temperature.
    I checked with another device.The result was 16.03MHz.
    There are variations in device MCLK characteristics.
    Does that mean that there can be devices with MCLK of 16.6MHz due to variations?
    Is the 16.6MHz device in the range of variation?
    case1:DCO only output(another device)
    case2:DCO&FLL Lock output(another device)
  • Hi K.saito,

    It seems that the MCLK frequency of this chip has exceeded the error range, and the accuracy data of the clock is attached.

    Is it possible to test more chips to determine weather only this chip is abnormal?

    Best Regards

    Johnson

  • Hi

    Thank you for the advice.

    For three devices, MCLK was output from P2.6 and the frequency was confirmed.
    No1.16.6MHz
    No2.16.03MHz
    No3.16.08MHz
    Q1Is the No.1 device broken?
       However, the No.1 device was 16.06MHz when the frequency after 1ms passed after the FLL lock was confirmed.
       Do you know what is happening?
    Q2.Is there a risk of a crash if I don't wait for the FLL lock?
    Comment out "while (CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));"
     
    #include <msp430.h>
    #define DCO_CALIBRATION_ADDR 0x1A22

    int main(void)
    {
        WDTCTL = WDTPW | WDTHOLD;                          // Stop watchdog timer

        // Configure one FRAM waitstate as required by the device datasheet for MCLK
        // operation beyond 8MHz _before_ configuring the clock system.
        FRCTL0 = FRCTLPW | NWAITS_1;

        P1DIR  = 0x01;
     P1OUT  = 0x00;
     P2DIR  = 0x40;
     P2OUT  = 0x40;//P2.6 MCLK OUT
     P2SEL0 = 0x40;//P2.6 MCLK OUT

        __bis_SR_register(SCG0);                           // disable FLL
        CSCTL3 |= SELREF__REFOCLK;                         // Set REFO as FLL reference source
        CSCTL0 = 0;                                        // Clear DCO and MOD registers
        CSCTL0 |= *(unsigned int *)DCO_CALIBRATION_ADDR;   // clear DCO and MOD registers
        CSCTL1 &= ~(DCORSEL_7);                            // Clear DCO frequency select bits first
        CSCTL1 |= DCORSEL_5;                               // Set DCO = 16MHz
        CSCTL2 = FLLD_0 + 487;                             // DCOCLKDIV = 16MHz
        __delay_cycles(3);
        __bic_SR_register(SCG0);                           // enable FLL
     //   while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));         // FLL locked


        CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;       // Set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                         // default DCOCLKDIV as MCLK and SMCLK source

        CSCTL5 |= DIVS_2 + DIVM_0;                       // MCLK = DCOCLK = 16MHz
                                                         // SMCLK = MCLK/4 = 4MHz

        PM5CTL0 &= ~LOCKLPM5;                            // Disable the GPIO power-on default high-impedance mode
                                                         // to activate previously configured port settings
        P1OUT |= 0x01;

        while(1)
        {
            __delay_cycles(8000);
        }
    }

  • Hi K.saito,

    According to your description, write calibration of 16MHz in TLV to CSCTL0 register, then enable FLL module waiting FLL locked, this method is should meet your require about fast start-up, Why do you want to Comment out "while (CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));" ?

    And what the means about "the No.1 device was 16.06MHz when the frequency after 1ms passed after the FLL lock was confirmed"?

    What is this test conditions? Write calibration value to CSCTL0 register and enable FLL?  This frequency of MCLK will become 16.06MHz after 1ms passed after executing this code( while (CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); )?

    Best Regards

    Johnson

  • Hi

    Since each device has a different lock waiting time, it may not be able to start in the worst case.
    So I wanted to see what would happen if I didn't wait for the lock.

    The worst sample No.1 shows the following trends.

    Timing 1 is 16.6Mhz in the following source code. On the other hand, the timing 2 is 16.03MHz.
    Why doesn't it become 16MHz with Timing1?
    What do you think is happening?

     

    Temperature condition: Indoor 25 ℃

    -Timing1

    -Timing2

    #define DCO_CALIBRATION_ADDR 0x1A22

    int main(void)
    {

        WDTCTL = WDTPW | WDTHOLD;                          // Stop watchdog timer

        // Configure one FRAM waitstate as required by the device datasheet for MCLK
        // operation beyond 8MHz _before_ configuring the clock system.
        FRCTL0 = FRCTLPW | NWAITS_1;

        P1DIR  = 0x01;
     P1OUT  = 0x00;
     P2DIR  = 0x40;
     P2OUT  = 0x40;//P2.6 MCLK OUT
     P2SEL0 = 0x40;//P2.6 MCLK OUT

        __bis_SR_register(SCG0);                           // disable FLL
        CSCTL3 |= SELREF__REFOCLK;                         // Set REFO as FLL reference source
        CSCTL0 = 0;                                        // Clear DCO and MOD registers
        CSCTL0 |= *(unsigned int *)DCO_CALIBRATION_ADDR;   // clear DCO and MOD registers
        CSCTL1 &= ~(DCORSEL_7);                            // Clear DCO frequency select bits first
        CSCTL1 |= DCORSEL_5;                               // Set DCO = 16MHz
        CSCTL2 = FLLD_0 + 487;                             // DCOCLKDIV = 16MHz
        __delay_cycles(3);
        __bic_SR_register(SCG0);                           // enable FLL
        while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));         // FLL locked


        CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;       // Set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                         // default DCOCLKDIV as MCLK and SMCLK source

        CSCTL5 |= DIVS_2 + DIVM_0;                       // MCLK = DCOCLK = 16MHz
                                                         // SMCLK = MCLK/4 = 4MHz

        PM5CTL0 &= ~LOCKLPM5;                            // Disable the GPIO power-on default high-impedance mode
                                                         // to activate previously configured port settings
       
        P1OUT |= 0x01;  //Timing1 Waveform
       
        McuDelayMillisecond(10); //10ms wait
       
        P1OUT &= ~0x01;//Timing2 Waveform

        while(1)
        {
            __delay_cycles(8000);
        }

    }

  • Hi K.saito,

    According to your description, it may be just a problem with this chip. You can test multiple chips to see if there are many chips.
    For the FR2110 chip with the highest frequency of 16MHz, we can't commit that there will be no unpredictable problems when MCU operation at 16.6MHz. Another method for this issue, If you have some space for your start-up time, could you consider add some delay after the FLL lock?

    Best Regards

    Johnson

  • Hi

    Thank you for your reply.

    I also checked the MCLK frequency of Timing1 and Timin2 for Four more devices.

    The devices confirmed by addition are No2 to No5.

    We need to assume that devices like No1 will be mixed in mass production.
    In that case, it may be better to use only the output of the DCO.

    No1

    No2

    No3

    No4

    No5

  • Hi K.saito,

    I test 14 pics in our lab use your code, and not found any problem.

    According to our test results, I have the following ideas:

    • Are you using our target board or your own hardware circuit during the test? Does the problem occur on the hardware circuit (or Crystal oscillator)?
    • Could you use more higher oscilloscope during test this chip? I found that the position of the cursor during the test is not very accurate.
    • It is possible to test more times for one chip because the MCLK clock is slightly fluctuating and there are errors in the measurement.
    • Could you garb the power waveform when you garb MCLK frequency? Because MCLK frequency maybe impact by power.

    Attach my test image : 

    More data about testing :

     2766.FR2110_1.zip 

    Best Regards

    Johnson

  • Hi K.saito,

    Due to the limitation of E2E uploading the largest attachment, I divided the test results into three uploads

    Part 2 :

    FR2110_2.zip

    Best Regards

    Johnson

  • Hi K.saito,

    Part 3 :

    FR2110_3.zip

    Best Regards

    Johnson

  • Hi

    Thanks for reply.
    We are using MSP-TS430PW20 as the development environment.
    We do not connect our own circuit. Evaluation board alone.
    A crystal oscillator is not used.

    The waveform was retaken with a highly accurate oscilloscope.

    Timing1:Blue clock, pink P1.0, green power supply (VCC)

    Timing2

    The worst sample was confirmed about 10 times, but the measurement result has not changed.

    Power is supplied to the target board from MSP-FET430UIF..
    The program is running from the debugger.

  • Hi K.saito,

    I contacted you on E2E by private message to further discuss this issue. I close this post and we can discussed this issue via email.

    Best Regards

    Johnson

**Attention** This is a public forum