• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 79 subscribers
  • Views 337 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSP430FR2533: About BOR

U-SK
Genius 5840 points
Part Number: MSP430FR2533

Hello,

I'm reading BOR section in page of 26 in Datasheet.

But I can't understand about BOR operation.

Is my following understanding correct?

Only If DVCC drops below (VBOR, safe), and kept low longer than (tBOR, safe) before it reaches VSVSH+, safe BOR is generated.

In safe BOR is being generated(after tBORsafe from at the time DVCC drops below VBORsafe), Device is in BOR reset state until DVCC reaches VSVSH+.

And I have three question.

1.How does the device measure tBOR time? (In the state of DVCC of 0.1V, logic such as counters in the device should not operate)

2.What is the trigger of Power Cycle Reset?

3.What is the difference between Power Cycle Reset, SVS Reset, BOR Reset and safe BOR in terms of the device state?

Regards,

U-SK

  • 0
    TI__Guru 60181 points

    Hello U-SK,

    Let me do a little research on this and get back to you.

  • 0 in reply to Dennis Lehman
    Genius 5840 points

    Hi Dennis,

    Thank you for your reply.

    Do you have any updates?

    Regards,

    U-SK

  • 0 in reply to U-SK
    TI__Genius 14165 points

    Hi U-SK,

    let me quickly jump in here!

    Yes your understanding is correct: The BOR (RESET) is only reliable executed and guaranteed if DVCC drops below (VBOR, safe), and kept low longer than (tBOR, safe) before it reaches VSVSH+.

    Regarding your  three question.

    1.How does the device measure tBOR time? (In the state of DVCC of 0.1V, logic such as counters in the device should not operate)
    -> Pls understand that we cannot disclose design details but I can tell it is not related on a logic counter but more to analog implementation related to delays which are required power down drop safely for certain voltage conditions. I'm note aware of a logic counter which can work at 0.1V.

    2.What is the trigger of Power Cycle Reset?
    Powering up the application from 0V for example by applying the battery first time.

    3.What is the difference between Power Cycle Reset, SVS Reset, BOR Reset and safe BOR in terms of the device state?
    Power Cycle RESET, BOR RESET and SVS and safe BOR will all generate a BOR which is the highest level reset in this device -> see also user guide chapter 1.2 System Reset and Initialization. However SYSRSTIV you can later on check what triggered the BOR (see datasheet chapter 6.10.5). This can help to understand what happens on the application.

**Attention** This is a public forum