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Part Number: MSP430FR2633
I am referring to following schematics.
EZFET_SBWTCK_TST, EZFET_SBWTDIO_RST signals seems to be marked with "X" on the "MSP430F5528 EZ-FET MCU".
EZFET_TXD, EZFET_RXD signals seems to be marked with "X" on the "MSP430F5528 EZ-FET MCU" and "PROGRAMMER EDGE CONNECTOR".
Does that mean they are disconnected? Or is it a typo?
When using a reset IC, how should the reset IC be connected to the EZFET_SBWTDIO_RST line?
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In reply to Yiding Luo:
Thank you for your reply.
Do you have any updates?
In reply to U-SK:
They are all connected and I think the "X" is how it shows in the schematic when you only have one side connected in the page.
Here are the connections:
On the PGMR board there are two MSP430F5528 devices:
On the PGMR/FR2633 "PROGRAMMER EDGE CONNECTOR" we have:
When you connect the PGMR and FR2633 MCU board together with the connector, these pins are connected:
If you want to use the EZFET_RXD and EZFET_TXD backchannel UART function you will need to disconnect the PGMR and FR2633 boards and use jumper wires to connect them.
For how to connect EZFET_SBWTDIO_RST line I will recommend to follow FR2633 MCU board design.
I understand each of EZFET_SBWTCK_TST, EZFET_SBWTDIO_RST, EZFET_RXD EZFET_TXD and EZFET_RXD EZFET_RXD signal is connected.
But I can't understand purpose of "X" in the schematics.
Are all signals with “X” connected to each other?
How about BRIDGE_TEST signal of MSP430F5528 in the following document?
I don't know why "X" is marked on the BRIDGE_TEST signal instead of the BRIDGE_TCK signal.
I am checking with the team who did the schematic about the "x".
In 2-wires SBW TCK is connected to TEST signal and for MSP430 we refer that pin as TEST/SBWTCK.
The "X" is a feature in Altium Designer to place a non-specific No ERC.
The No ERC object is a design directive. It is placed on a node in the circuit to suppress all reported Electrical Rule Check warnings and/or error violation conditions that are detected when the schematic project is compiled. Use No ERC to deliberately limit error checking at a certain point in the circuit that you know will generate a warning (such as an unconnected pin) while still performing a comprehensive check of the rest of the circuit.
Since some of the pins are only connected at one end on the schematic so we use this feature to limit the error checking message during development.
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