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MSP430FR5949: ADC/Timer Misbehavior

Prodigy 220 points

Replies: 7

Views: 224

Part Number: MSP430FR5949

Dear team,

I am using MSP430FR5949/47 in my project. My application is to read analog data and send them to external medium upon request from other side through serial port.

I have timerA3 ISR for every 50uS (Timer clock is SMCLK initialized for 8 MHz) and SCI receive ISR.

Initialized ADC to convert single channel at a time. In Timer interrupt, polling for ADC Conv Flag and reading results.

After receiving data request from other end , I am transmitting data on serial port.

In some cards, the other end device is receiving freezed data after some time.

Here my doubt is:

1. Is ADC is stopped converting after some time? So, ADC Flag will not set and data is not getting loaded into my internal variable

or

2. As TimerA3 has least priority compared to Serial ISR, Timer ISR is not getting triggered due to repeated serial ISRs

  • Hi Sai,

    You can run in debug mode to locate the execution of the program when the problem (end device is receiving freezed data) occurs, and observe the related register, which is convenient for analysis.

    Best Regards

    Johnson

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    If my reply answers your question please click on the green button "This resolved my issue".

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  • In reply to Johnson He:

    Hi Johnson,

    Thanks for reply

    The problem observed only in some cards in the field.

    Unable to use debugger in field.

    From device errata,  ADC42:

    In manual trigger mode,  it is required to ensure each ADC conversion by first checking adc12busy bit before starting in new conversion

    Here I'm using single channel at a time,  after checking ADC12_B_IFG0 only loading results into my local variable and starting conversion of next channel without checking for ADC12BUSY flag.  In datasheet given ADC12BUSY will be set when a sequence, sample or conversion is active.  I'm giving trigger to next channel after reading previous result.

    1. Is there any chance of ADC12BUSY bit remains set even after ADC12_B_IFG0 is set

    2. Is it necessary to ensure ADC12BUSY bit is clear before starting next sampling and conversion in single channel manual triggering mode

  • In reply to Sai Kiran Reddy Patlolla:

    Hi Sai,

    As the description of ADC42 in Errata,

    "ADC stops converting when successive ADC is triggered before the previous conversion ends"

    This affected ADC modes : sequence-of-channels, repeat-single-channel and repeat-sequence-of-channels.

    If you setting ADC12CONSEQx register to 00(Single-channel, single-conversion), this is not affected by this errata.

    For your first question :

    ADC12BUSY is set in active sample or conversion operation, and the ADC12_B_IFG0 will set in complete this conversion, so this The situation you describe does not occur.

    For your second question :

    You need to check the ADCBUSY bit is low, then start next sampling and conversion. Use this way to ensure the correctness and accuracy of the ADC conversion.

    Best Regards

    Johnson

    Search E2E! Your questions may already be answered! 

    If my reply answers your question please click on the green button "This resolved my issue".

    Useful pages: TI Cloud Tools             MSP Product Page

  • In reply to Sai Kiran Reddy Patlolla:

    Hi Sai,

    I haven’t heard from you for seven days, so I’m assuming you were able to resolve your issue. If this isn’t the case, please click the "This did NOT resolve my issue" button and reply to this thread with more information. If this thread locks, please click the "Ask a related question" button and in the new thread describe the current status of your issue and any additional details you may have to assist us in helping to solve your issues.

    Best Regards,

    Johnson

    Search E2E! Your questions may already be answered! 

    If my reply answers your question please click on the green button "This resolved my issue".

    Useful pages: TI Cloud Tools             MSP Product Page

  • In reply to Johnson He:

    Earlier there are two interrupts in my software. One is timer isr and other one is sci receive isr. After some time timer isr is not getting triggered . From device data sheet , sci isr has highest priority compared to timer a3 isr. So, there might be chance of timer isr not getting serviced due to repeated sci receive isr. Then later removed sci receive isr and used timer a3 isr. In my application there are 8 adc channels to be read and need to send the data based on request from master.  Software flow is as follows, in timer isr, triggering single adc channel, based on adcifg, reading the result and giving trigger to next channel. This continues till 8 channel, after reading 8 channel result giving trigger to first channel. Upon request from master I.e., scirxflag is polled in timer isr, when flag is set sending data to master. In some cards upon request from master sending freezed data. My doubt is why adcifg is not getting set. If adcifg flag is set, then converted value will be loaded to internal buffer and freezed data will not be sent to master.

  • In reply to Sai Kiran Reddy Patlolla:

    Hi Sai,

    Do you means that the ADCIFG not setting when enable ADC sample in TIMER interrupt?

    Could you provide some details about this issue?

    Such as : code related to TIMER/ADC interrupt and configuration.

    Best Regards

    Johnson

    Search E2E! Your questions may already be answered! 

    If my reply answers your question please click on the green button "This resolved my issue".

    Useful pages: TI Cloud Tools             MSP Product Page

  • In reply to Sai Kiran Reddy Patlolla:

    Hi Sai,

    How about your issue?

    Best Regards

    Johnson

    Search E2E! Your questions may already be answered! 

    If my reply answers your question please click on the green button "This resolved my issue".

    Useful pages: TI Cloud Tools             MSP Product Page

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