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MSP430F5359: Errata PMM12

Part Number: MSP430F5359

The errata for the MSP430F5359 is located here: http://www.ti.com/lit/er/slaz495z/slaz495z.pdf.

From that doc, PMM12 is the following:

SMCLK comes up fast on exit from LPM3 and LPM4

The DCO exceeds the programmed frequency of operation on exit from LPM3 and LPM4 for up to 6 us. When SMCLK is sourced by the DCO, it is not masked on exit from LPM3 or LPM4. Therefore, SMCLK exceeds the programmed frequency of operation on exit from LPM3 and LPM4 for up to 6 us. The increased frequency has the potential to change the expected timing behavior of peripherals that select SMCLK as the clock source.

Workaround

- Use XT2 as the SMCLK oscillator source instead of the DCO. OR

- Do not disable the clock request bit for SMCLKREQEN in the Unified Clock System Control 8 Register (UCSCTL8). This means that all modules that depend on SMCLK to operate successfully should be halted or disabled before entering LPM3 or LPM4.If the increased frequency prevents the proper function of an affected module, wait 32, 48, 64, or 80 cycles for core voltage levels 0, 1, 2, and 3, respectively, before re-enabling the module [for example, __delay_cycles(32)].

My question is: If SMCLK is being used in an SPI peripheral, do we need to hold the peripheral in reset while in LPM3 or LPM4, or is it enough to wait the appropriate number of cycles before trying to send any data over SPI. In this case, the MSP430 would be the master of the SPI bus so there should be control over when the data is sent (consequently, when the clock is needed to drive SCK).

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