msp430fr5992 Clock System

Problem phenomenon: normally, the baud rate of the product is 9600 after power on, but sometimes the baud rate changes to 4800 after power on.


Product Description: MCU is msp430fr5992, LF is external 32.768k, HF is external 12M, aclk = LF, smclk = HF, MCLK = DCO (21mhz, due to large amount of program calculation, 21m must not be used). LF and HF are not connected to the ground capacitance. After power on, the baud rate of the product is fixed to 9600. After power on, the baud rate can be modified to 480096001920038400 by command. However, power off is not saved.

Phenomenon: sometimes the data output by the serial port cannot be parsed at 9600 baud rate after the product is powered on. It is found that the reason is that the baud rate is not 9600. Most of the actual baud rate is 4800, which is twice smaller than the actual value. Occasionally there are other values, once it is 1920, which is 5 times smaller than 9600. But it can be restored to 9600 after power failure and restart.

My own testing process:

1. Output the values of registers uca0brw, uca0ctlw0 and csctl3 through the serial port, and check whether the configuration value has been modified.

Results: when the baud rate is 4800 after power on, the value of uca0brw is still the corresponding value of 9600. The value of uca0ctlw0 also indicates that the clock source of the serial port is smclk, and the value of csctl3 also indicates that the frequency division value of smclk is 1, and the real-time clock has no frequency division. These values are exactly the same as those of normal power on.

2. When the upper radio frequency special rate is 4800, the baud rate is modified by the command of modifying baud rate in the product. After sending the command of setting 9600 baud rate under 4800, the actual baud rate is still 4800. After sending the command of setting 4800 baud rate, the actual baud rate changes to 2400 (there is no code configured for 2400 baud rate in the program). After sending the command of setting 38400 baud rate, the actual baud rate is 19200, that is to say, the actual baud rate after setting is half lower than expected.

3. There is an LED with a flashing period of 1s on the product, which is made by timer. The clock source of timer was originally 32.768, and the clock source of timer was changed to smclk. When the baud rate of the product was 4800 after power on, it was found that the flashing period of LED was changed to 2S.

4. When the baud rate is 4800 after power on, use an oscilloscope to measure the HF value, which is 12m.

5. Output all the registers csctl1-csctl6 of the clock with serial port. There is no difference between the values when the power on is normal and the power on radio frequency is 4800.

6. Add a test program to call clock initialization and serial port initialization through the command. When the baud rate is 4800 after power on, send the command to reinitialize the clock and serial port without any change.

7. When the baud rate is 4800 after power on, execute the command pmmctl0 = pmmpw + pmmswpor (that is, trigger a POR through software), and the baud rate can be restored to 9600


Based on the above tests, I personally think that the value of smclk is divided by 2, but I don't know where it is divided. By observing the frequency division register display, there is no frequency division. In addition, there is a 5-frequency division. Even if it is realized through the frequency divider, the frequency division multiple is not 5 times. It is 2 / 4 / 8 . In addition, even if the clock setting or serial port setting is modified, why the reset initialization function does not work. And why can a software por restore the baud rate to 9600? Is it equivalent to power on again.


Void CLK init (void) / / clock initialization

{


FRCTL0=0XA500+NWAITS0+NWAITS1+NWAITS2;

PJDIR=0x00;

PJOUT=0;

PJREN=0xFF;

Pjsel0 = pjsel04 + pjsel05 + pjsel06 + pjsel07; / / low frequency crystal oscillator selection

PJDIR|=(BIT5+BIT7);

CSCTL0=0xA500;//password

CSCTL1=DCOFSEL0+DCOFSEL2+DCORSEL;

CSCTL2=0;

CSCTL2=SELS0+SELS2+SELM0+SELM1;//ACK=LFXT 01=MCLK=DCOCLK

Csctl3 = 0; / / divm0; / / ACK smclk smclk frequency division number is 1

Csctl4 = vlooff + lfxtdrive0 + lfxtdrive1 + hfxtdrive0 + hfxtdrive1 + hffreq1; / / close VLO


CSCTL5=0;

CSCTL6=ACLKREQEN+MCLKREQEN+SMCLKREQEN+MODCLKREQEN;//

Do

{

PM5CTL0 &= ~LOCKLPM5;

CSCTL0=0xA500;//password

CSCTL0_H=0xa5;

CSCTL5 &= ~(LFXTOFFG+HFXTOFFG);

SFRIFG1&=~OFIFG;

delay(0xfff);

}

while(SFRIFG1&OFIFG);

}


In addition, hundreds of sets of this product have been produced. At present, this problem has been found on one board.


Please point out what will be the cause of the experts, confused for several days, thank you!