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MSP430F147: SPI Data Missing bits/shifted problem

NURUL SYAFIQAH ABD RAZAK
Prodigy 10 points
Part Number: MSP430F147

Hi,

We are using MSP430147, be connected that will loop data back to the SPI Master (the CPLD).

The raw clock signal coming into the CPLD has Freq: 1.85 MHz, Prd: 542 ns.

The SCLK signal path is as below :

 

               Raw clock ( 542 ns ) => 1/20 Clock divider => 1/4 period when SCLK is generated

 

               So 543 ns * 20 * 4 = 43.36 us.

But there are missing bits when reading back the data. For example, the write data is "AAAAAA" but the readback data is "555554".

The data waveform that goes into the pin 20 and pin 21 of the MSP as below:

and the waveform from MSP to CPLD as below

:

 

From the result, the read and write data is shifted and not tally.

What are the possible reasons that this issue happens and what are the countermeasure that could be made to solve it?

 

Thanks!.

 

  • 0
    Guru 88490 points

    For a symptom like this, the first thing to check is the clock phase (CPHA). For CPHA=0, you should set UCCKPH=1 (and vice versa).

    While you're in there, check the polarity (CPOL) as well. For CPOL=0, you should set UCCKPL=0 (and vice versa). (This isn't the usual symptom for CPOL, but you might as well make sure.)

    A "remote second" suspect is cable length. A long (say 150mm) cable can produce this symptom at 4MHz; I don't have experience with longer/slower combinations. The fix for this would be to slow the SPI down, but 23kHz is already pretty slow.

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