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MSP432E411Y: LCD DMA priority and setting

Part Number: MSP432E411Y

Dear Champs,

About LCD DMA, here are some problems that hope to confirm it. 

1. Is LCD DMA independent with uDMA? 

2. If yes, how do we set LCD DMA priority? 

3. On 20.3.2.1.2 Raster Mode section, it said DMA engine generates the interrupts. How to arrange the priority of LCD DMA interrupt?

If you have any suggestions, please feel free to let me know.

Thanks a lot.

Best rregards,

Janet

  • Hello,

    Janet Shen said:
    1. Is LCD DMA independent with uDMA? 

    Yes, the LCD DMA engine is independent from the uDMA module.

    According to the datasheet, the DMA controller is known as micro-DMA (µDMA). The µDMA controller provides a way to offload data transfer tasks from the Cortex-M4F processor, allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform transfers between memory and peripherals. It has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data.

    The LCD controller has its own dedicated high-priority DMA engine, so it doesn't have to steal cycles from the micro DMA (uDMA) module in the system. The LCD DMA engine has a small FIFO, and it allows periodic interruptions as necessary.

    Janet Shen said:
    2. If yes, how do we set LCD DMA priority? 

    The LCD DMA engine interrupts all seem to be high priority but don't seem to be prioritized over each other. I assume that's because these interrupts are only related to the LCD module, or this could imply that the LCD module doesn't work properly when any one interrupt is set. I would focus less on the priority and instead understanding how to address the scenario represented by each interrupt.

    Janet Shen said:
    3. On 20.3.2.1.2 Raster Mode section, it said DMA engine generates the interrupts. How to arrange the priority of LCD DMA interrupt?

    Please see my comments for Question 2.

    Regards,

    James

  • Dear James,

    If we hope LCD DMA priority is highest than EPI and uDMA, how do we do? 

    Because we met a problem for LCD display flicker when EPI write big data to SDRAM.

    We have enabled LCD DMA and double buffer but no improvement. Could we let LCD DAM priority as the highest priority?

    If you have any suggestions, please feel free to let me know.

    Thanks a lot.

    Best regards,

    Janet

  • Hi Janet,

    The LCD DMA and uDMA are separate. If you look at the uDMA table in the datasheet, there isn't an LCD option. It sounds like there's an issue with the LCD configuration, so I wouldn't worry about the priority. Do the LCD DMA interrupt flags indicate the issue?

    Regards,

    James

  • Dear James,

    Please kindly look at the register current values for LCD DMA when coding running.

    If you have any suggestions, please feel free to let me know.

    Thanks a lot.

    Best regards,

    Janet

  • Hi Janet,

    Thanks for sharing those. I see that LCD_RISSET_FIFOU is set to 1. According to the TRM, this means that the LCD DMA engine cannot keep up with the data rate consumed by the LCD. That data rate is determined by the LCDCP setting. This is likely due to a system memory throughput issue or an incorrect LCDCP setting. The FIFOU bit in LCD Interrupt Raw Status and Set Register (LCDRISSET) register is set when this error occurs.

    I see LCD_DMACTL_FIFORDY is set to 0x6 (512 words) and LCD_DMACTL_BURSTSZ is 0x4 (Burst size of 16). That seems to be the max transfer amount, so it's possible that there's not enough time for the LCD DMA to transfer everything in one period of the LCD data rate. Try adjusting the LCDCP settings.

    Regards,

    James

  • Dear James,

    Yes, I tried to change LCDCP as below from 30000000 (30MHz) to 6000000 (6MHz). But it issue still existed.

    MAP_LCDModeSet(LCD0_BASE, LCD_MODE_RASTER|LCD_MODE_AUTO_UFLOW_RESTART, 6000000,ui32SysClock);

    Hence, I still suppose LCD DMA setting have something wrong. Do you have any suggestion for the setting of LCD and LCD DMA engine?

    Please feel free to let me know any idea.

    Thanks a lot.

    Best regards,

    Janet

  • Hi Janet,

    What is the SysClock frequency?

    In raster mode, ui32PixClk specifies the pixel clock rate for the raster interface and valid values are between ui32SysClk/2 and ui32SysClk/255. The actual clock rate set may differ slightly from the desired rate due to the fact that only integer dividers are supported.

    Regards,

    James

  • Dear James,

    The system clock is 120MHz.

    Except reduce pixel clock, do you think which workaround can I try?

    If you have any suggestions, please feel free to let me know.

    Thanks a lot.

    Best regards,

    Janet

  • Hi Janet,

    Thanks for sharing those details. Looking back at your initial post, I'm wondering if you were asking about changing interrupt priorities related to the NVIC rather than the different DMA interrupt priorities.

    The interrupt priorities are discussed in the datasheet (Section 6.3.3) and TRM (Section 2.2.2). Also, I found in the DriverLib API guide that the APIs IntPriorityGet() and IntPrioritySet() could be used to read an interrupt priority and then change that priority.

    Regards,

    James

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