MSP430FR5969: Timer Delay 30 seconds

Yes. Its working. 

So, from timer settings, I have verified that the System Clock is clock divided by Input Divider for 2 circuits(TA0CTL0 |= ID_3; along with TA0EX0 |= 0x07;)

Is there any change in Clock System input Divider?

TA0CCR0 = 4100; //VLO = 8.7KHz; (8700/8/8)*30;
TA0EX0 = 0x07;
TA0CCTL0 = CCIE; // Timer interrupts enable
TA0CTL = TASSEL_1 + ID_3 + MC_1 + TACLR; // Timer0_A

This is my code. I found that, 30 accuracy is obtained for 8.7KHz w.r.t calculation mentioned above. But in datasheet, typical VLO frequency is 9.4 KHz. How to get accurate results with typical frequency.

The VLO is notoriously inaccurate (but it's cheap!).

One thing you can do is measure its speed based on a known reference, e.g. SMCLK or crystal (LFXT) and use that to compute the delay constant.

There are Application Notes about this for the F2 and FR2 series -- one uses SMCLK and the other the RTC. Code is available via a link in the PDF. 

https://www.ti.com/lit/an/slaa340a/slaa340a.pdf

https://www.ti.com/lit/an/slaa693a/slaa693a.pdf

Keep in mind the temperature drift in Table 5-7. Also, on some devices it changes when you go into LPM3 [I've forgotten where I saw this] so measure it in the mode you'll be using.