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MSP430F6736: SD24 Linearity Issue

Avishai Henley1
Prodigy 30 points
Part Number: MSP430F6736

Hi,

I came across a non-linearity in the SD24 performance.

See below:
ch 0 

ADC reading (dec) ADC reading (dehex) Vref Vin (mv) ADC/Vin ADC/Vin/Vin(1)
12784781 C3148D 1.24 640 19976 1.00
13817630 D2D71E 1.24 790 17491 0.88
14840565 E272F5 1.24 956 15524 0.78
15713836 EFC62C 1.24 1084 14496 0.73
15974404 F3C004 1.24 1123 14225 0.71
16066820 F52904 1.24 1170 13732 0.69



It looks as if the ADC/Vin is not constant as should be, but kind of reduces as Vin is higher (see above)
Vin was measured with DMM on the MSP input.

See below the register dump:
Reg Group Reg Name Reg Value (Hex) Value Meaning
SD24BCTL0 0x1B10
SD24DIVx 3 3
SD24PDIVx 3 8
SD24CLKOS 0 fM
SD24M4 0 fM=fM=fSD24
SD24SSEL 1 SMCLK
SD24REFS 0 Ext Ref (In released SW: internal. Short between internal and ext)

SD24BCTL1 0x802
SD24DMAx 0b1000 SD24TRGIFG triggers DMA
SD24GRP3SC 0 No conv_start for group 3
SD24GRP2SC 0 No conv_start for group 2
SD24GRP1SC 0 Start conversion for group 1
SD24GRP0SC 0 No conv_start for group 0

SD24BIFG NA (read only interrupt status)

SD24BIE 0x4
SD24IE2 1 Converter 2 interrupt enable
SD24IE0,1 ; SD24OVIE2..0 0 No overflow interrupts enabled, no converter 0,1 interrupts enabled

SD24BIV NA (Read only)

SD24BCCTLx 0x000B
SD24MC 0 Bitstream synchronous to fM. Output data changes with falling clock edge, input data is captured with rising clock edge.
SD24DI 0 Bitstream from modulator fed into digital filter
SD24DFS 0 SINC3 filter
SD24CAL 0 Calibration disabled.
SD24SNGL 0 Continuous conversion mode
SD24ALGN 0 = Right-aligned. LSB of filter output is bit 0.
SD24DF 00b Offset binary
SD24SCSx 101 Group 1 - Start of conversion defined by SD24GRP1SC bits in register SD24BCTL1
SD24SC 1 NA: Conversion ongoing indication

SD24BINCTLx 0x0
SD24INTDLYx 00b Fourth sample causes interrupt
SD24GAINx 000b Gain = 1

SD24BOSRx 0xff
SD24OSRx 0xff Oversample = 255+1 = 256

SD24BPREx 0x14
SD24BPREx 0x14 Digital filter preload value = 0x14 = 20


The outputs of the ADCs (SD24 0 to 2) is sampled in rate of 25Hz.

Can you advise as for the reason of the non-linearity?

It looks as if the ADC/Vin is not constant as should be, but kind of reduces as Vin is higher (see above)
Vin was measured with DMM on the MSP input.

See below the register dump:
Reg Group Reg Name Reg Value (Hex) Value Meaning
SD24BCTL0 0x1B10
SD24DIVx 3 3
SD24PDIVx 3 8
SD24CLKOS 0 fM
SD24M4 0 fM=fM=fSD24
SD24SSEL 1 SMCLK
SD24REFS 0 Ext Ref (In released SW: internal. Short between internal and ext)

SD24BCTL1 0x802
SD24DMAx 0b1000 SD24TRGIFG triggers DMA
SD24GRP3SC 0 No conv_start for group 3
SD24GRP2SC 0 No conv_start for group 2
SD24GRP1SC 0 Start conversion for group 1
SD24GRP0SC 0 No conv_start for group 0

SD24BIFG NA (read only interrupt status)

SD24BIE 0x4
SD24IE2 1 Converter 2 interrupt enable
SD24IE0,1 ; SD24OVIE2..0 0 No overflow interrupts enabled, no converter 0,1 interrupts enabled

SD24BIV NA (Read only)

SD24BCCTLx 0x000B
SD24MC 0 Bitstream synchronous to fM. Output data changes with falling clock edge, input data is captured with rising clock edge.
SD24DI 0 Bitstream from modulator fed into digital filter
SD24DFS 0 SINC3 filter
SD24CAL 0 Calibration disabled.
SD24SNGL 0 Continuous conversion mode
SD24ALGN 0 = Right-aligned. LSB of filter output is bit 0.
SD24DF 00b Offset binary
SD24SCSx 101 Group 1 - Start of conversion defined by SD24GRP1SC bits in register SD24BCTL1
SD24SC 1 NA: Conversion ongoing indication

SD24BINCTLx 0x0
SD24INTDLYx 00b Fourth sample causes interrupt
SD24GAINx 000b Gain = 1

SD24BOSRx 0xff
SD24OSRx 0xff Oversample = 255+1 = 256

SD24BPREx 0x14
SD24BPREx 0x14 Digital filter preload value = 0x14 = 20


The outputs of the ADCs (SD24 0 to 2) is sampled in rate of 25Hz.

Can you advise as for the reason of the non-linearity?

  • 0
    TI__Mastermind 49692 points

    Hello,

    Keep in mind that the datasheet recommends that the input voltage range is kept to ~80% of the reference voltage. As you can see in Figure 5-20 in the datasheet, the performance drops significantly when that threshold is crossed.

    Regards,

    James

  • 0 in reply to James Evans
    Prodigy 30 points

    Hi, Thanks!

    Its still odd.....

    When I added an "ADC error" column, it looks as if the error is larger on low_Vin than in high_Vin. See below:

    ADC reading (dec) ADC reading (hex) Vref Vin (mv) ADC/Vin Vin/Vref Expected ADC Error
    12784781 C3148D 1.24 640 19976 0.516 8659208 0.48
    13817630 D2D71E 1.24 790 17491 0.637 10688710 0.29
    14840565 E272F5 1.24 956 15524 0.771 12934692 0.15
    15713836 EFC62C 1.24 1084 14496 0.874 14666534 0.07
    15974404 F3C004 1.24 1123 14225 0.906 15194204 0.05
    16066820 F52904 1.24 1170 13732 0.944 15830115 0.01

    Please advice,

    Avishai

  • 0 in reply to Avishai Henley1
    TI__Mastermind 49692 points

    Hello,

    I do not recommend exceeding 0.992 V for Vin based on the guidelines in Footnote 2 under Table 5-35 in the datasheet. My comments will address what you're seeing for input voltages less than this limit.

    Are you doing this testing on your own custom hardware or are you using one of our target socket boards? If it's a custom board, have you followed all the recommendations in the datasheet for external capacitors, etc.? Also, these devices require several external connections to be made between certain pins (e.g. VDSYS).

    Do you see this behavior with the internal voltage reference?

    Do you see this behavior using one of our code examples?

    You may want to measure the offset on each ADC channel and apply that to your measurements.

    Also, keep in mind that the external source impedance does affect the settling time. Make sure your circuitry and settings aren't exceeding the minimum settling time discussed in Section 29.2.6.3 Analog Input Characteristics in the MSP430x5xx and MSP430x6xx Family User's Guide.

    Regards,

    James

  • 0 in reply to James Evans
    Prodigy 30 points

    Hi,

    1. I will follow the max Vin

    2. I aligned the caps to confirm to the requirements, but no change was observed. 

    3. The external pins are connected correctly

    See graph (red - expected. blue - actual)

  • 0 in reply to Avishai Henley1
    TI__Genius 14165 points

    Hi Avishai,

    you use 1 MHz for the modulation frequency and you see larger error and smaller input values. So what is is your RS and it this matching the minimum settling time requirements:

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