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MSP430F67791A: SD24B Best ENOB performance

Part Number: MSP430F67791A
Other Parts Discussed in Thread: EVM430-F6779, , MSP-TS430PEU128, MSP-FET

Hi we are assessing performance of the SD24B using the "EVM430-F6779 - 3 Phase Electronic Watt-Hour EVM for Metering" Demo Board, we set the SD24B to use the following settings:

Fm = 1.8432MHz

OSR = 512

Bits per reading = +/- 2^27 bits.

Vref = 1.25V +/- 1mV (external)

We have modified the 3 voltage channels (CH0:2) and shorted each of the channels together in order to obtain , the unit is powered from a low impedance battery (DVcc = 3V) 

The best ENOB that we could achieve using this setup was approximately 16 bits (which after some searching seems consistent with what others have experienced).

However the channel offset is not consistent between reads, it seems to drift +/- 4000 counts is this also to be expected?

I would of expected some variation of offset between channels,  but I did not expect the offset to be dynamically changing by such a large amount in a stable environment.

Any help or insight would be greatly appreciated 

  • Hi,

    How can you get ENOB with 16bits?

    I don't think the drift is to be expected. How can you know this problem lies on the channel offset?

    Can you share more data?

    Eason

  • Hi Eason,

    The ENOB is 16 bits (and generally closer to 17 bits) as the Vrms noise of the readings is up to 3,000 counts.

    The ADC inputs are shorted together, but taken out of the equation by setting the calibration bit (SD24CAL).

    The offset is consistent for a single read of the channel, but rerun the read and the offset can move.

    Also, the read has +/-5,000 counts of noise - is this level of noise usual for the SD24_B with the calibration bit set?

    Regards,

    Rob

  • Hi,

    I think Carl is trying to ask this.

    Why on repeated runs, with nothing changed, are we seeing samples like this?

    This is 10 runs of 360 samples with the input short circuited.

    Why does the average jump around?

    Is this amount of noise normal?

    This is critical to our project and we need a solution urgently.

    Thanks

    Jason

  • Furher examples of the offset shift are in the attached doc.

    Regards,

    Rob

    2020-08-18 Three 1s runs - offset shifting.docx

  • Sorry, I was on business travel.

    I have a question that for 24 bit SD ADC. Why you use +/- 2^27 bits to represent the result? Are you make a mistake?

    As we know the input signal, power supply, SD ADC itself and the reference will influence the result. 

    • Can you give a explain why you use Vref = 1.25V +/- 1mV (external), for internal reference (2.47-2.55V) it seems perform better than the external reference.
    • For power, as it is source from battery, I think it is good. How about  the reference? Does them keep stable? 
    • For the test result, If SD24GAIN = 1, the drift should be smaller than 2.3mV. But what I find is that the largest one (198000) is almost 3mV! What about  testing with the ADC inputs shorted together, and not setting the calibration bit (SD24CAL). 
    • Can you give me a explain how you test? What about the software setting? What about the hardware setting?  As I know on EVM430-F6779, there are some passive components between ADC + and ADC -. Can you test the drift by removing the passive components.

    Eason

  • Hi Eason,

    I hope the travel went well.

    +/-2^27 is used as that is what the SD24_B outputs when the OSR is set to 512.  SLAU461F SD24_B Section 1.2.7.3 Digital Filter Output details this:

    • The full-scale value output by the SINC3 digital filter is dependent on the oversampling ratio OSR and is given by FS = 2^(3×log2(OSR)). In offset binary mode, the full-scale range is from 0 to FS. In twos-complement mode, the full-scale range is from -FS to +FS.

    2^(3×log2(512)) = 134217728
    Log2(134217728) = 27bits = FS

    We are using twos-complement mode, so have a full-scale range of –FS to +FS, +/-27bits.

    In the MSP430F67791A datasheet, Table 5-51 REF Built-In Reference gives a range of 1.151V to 1.174V for the SD24_B internal reference voltage, VSD24REF, a range of +11.7mV/-11.3mV.  Due to this we switched to an external reference.

    The 2.47-2.55V is the VREF+ range (+/-40mV), is this also used in the SD24_B?

    The external reference is op-amp buffered with 270R between the op-amp and the 100nF VREF cap on the EVM430-F6779 (to decouple the capacitive load from the op-amp).

    Not setting the cal bit makes no discernible difference – the largest offset is still ~200000.

    We are using SD0, SD1 & SD2: V1, V2 & V3 of the EVM.  For each channel the series 1k resistors have been removed, the differential capacitor removed and the common mode capacitors replaced with 33nF.  The inputs are then short circuited across the resistor pads connected to the microcontroller (i.e. bar the capacitors, the passive components have already been removed from the EVM).

    Regards,

    Rob

  • Hi Rob,

    Thank you for your quick response.

    1. The reason why I ask why you use 27 bit is that. With 512 OSR, the ENOB will be about 16bit, normal we only take 16bit result. thank you for your explain.

    2. Sorry, I make a mistake about internal reference. Thank you for pointing it out. 

    3. I consult my analog design colleague, normally, the offset voltage should not change after a few time the ADC set up. So my suggestion is that:

    • Can you use internal reference to make the same test? As the input signal is OK, if it has the same condition, then it may lies on ADC itself.
    • For now, please add a code of calibration after the system power up first to work around this problem.
    • Please send your code to me, I can test them on my board (MSP-TS430PEU128) and double check if it is really a problem.

    4. By the way, what's your application by using F67791A? Detect DC voltage? If you use to measure AC voltage, you can use a DC filter, than you will not take the offset into consideration.

    Eason

  • Hi Eason

    Rob is on leave at the moment so I will answer some of your questions.

    As a bit of background the three engineers working on this are all extremely experienced with ADCs and DSP each with 20+ years experience.

    1. We need at least 19 bit accuracy. We were hoping that the MSP 24-bit ADC could achieve this even if we have to do a lot of filtering and averaging in software. In order to extract the very best the ADC can provide we will not be truncating the result until the very end. 

    3. The we have exactly the same results with internal and external references.

    Taking the offset calibration at power up is not a fix. The offset moves over a period of 100ms. We would need to calibrate before every reading. This is not acceptable.

    How should we send you the code (we don't want to put it on a public forum)?

    4. We are measuring DC with some AC present.

    Jason

  • Hi Jason,

    1. Can you accept a slow sample rate after you add averaging?

    2. Can you reach our TI Sales?He can find my e-mail address? I will loop other experts to help solve your question.

    Eason

  • Hi Eason

    1. Yes it's part of our design to acquire 200+ samples before performing software DSP. The problem is if we average say 200 samples (with the inputs short circuit, internal ref) the average is different, by a lot, each time.

    2. Rob has a support case open but they've asked us to use the forum. When Rob gets back he should be able to get your email address through the support ticket.

    Jason

  • No problem from my side.

  • Hi,

    It costs me some time to setup the hardware... I do some test based on F67791 and MSP-TS430PEU128.  The setup difference is that:

    1. Use internal reference

    2. Use internal refclock

    3. Power supply use MSP-FET

    See from the result, the noise Vpp is same as yours test, but I don't see a drift of the signal.

    Here is the data:

    test.xlsx

  • It is quite strange. I have no idea. I also check the Errata, there is no content about this problem. I will try to test the same chip as yours but it will cost more time to get the same chip.

  • Thank you for trying this.

    I think you are seeing at least a similar problem with your setup.

    Whilst CH2 and CH1 are consistent, if you look at CH0 repeated runs have a different average value. The shift in your data looks to be approximately 5,000 counts. We see around 10,000 counts but this could be a variation in hardware from device to device.

    We worry that a shift like this in the lab, at room temperature with only seconds between runs could become a lot worse in a product in the field.

    It seems that you have confirmed that the SD24 does have an inbuilt drift problem.

    Does anyone at TI have an idea of what is causing this and what we might be able to do about it?

  • Hi,

    I make an average of these 10 result. It has about 4000 different counts. You can also download the file and see mine test result. And the error caused is between 15 bit and 16 bit. Yes, you are right, it will add about 1 bit error to a 16 bit ENOB SD_ADC.

    122512.7 125459.6 122149.1 125592.2 122411.5 126298.1 122794.8 126391.5 122630.6 125720.5

    I will forward this question to my colleague.

    Eason

  • My colleague give an idea that: it may lies on the reference voltage setup, but see from you code, it is not lies on this problem.

    I make a further test. In the first test, I test CH0 first. In the second test, I test CH2 first. I make an average of 360 samples of one time. You can see that there is a regularity in the offset drift. Can you double check on your side? Maybe it is a break through point.

  • Yes, we also see offsets at different levels for each channel – no matter the order, the offset for a channel is approximately the same each run.


    The problem is the shift of this offset (which was just over 4000 counts for CH0 in test.xlsx).

  • Hi,

    I double checked with my colleague. He also has no idea about the drift problem.

    The thing is that, it seem related to the ADC hardware. There is no way to handle the drift. It is an old device, I also can't find the designer.

    I hope you can solve the problem from engineering perspective. My advice is that:

    1. Use external SD-ADC: it can easily reach 19bit resolution.

    2. Use internal SD-ADC: Calibrate at power up and don't turn off SD-ADC. Keep it working.

    Eason

  • Eason

    Yes we've come to the same conclusion. We were dearly hoping it was something we were doing wrong but it seems to be a 'feature' of the SD24B.

    As you suggest we're going to keep the ADC on and calibrate it each time we use it. If that doesn't work out it'll be an external ADC (which is what we've had to do in previous products).

    Thanks for trying.

    Jason

  • OK, I will close this thread.

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