MSP430F5529 ADC12SHSx

Hi Charles,

They managed to bury it pretty good in there.  See table 13 and table 16 in the "output pin number" columns.

ADC12 SHSx for '5529:

1 = TA0CCR1

2 = TBCCR0

3 = TBCCR1

 

Hello Jeff,

      Thanks for pointing that out.

      I am assuming that the reference to (internal) implies that it is an output of the TA0 but does not need to be on an output pin as the column "output pin number" implies.  Also what are you thoughts on configuring TA0 to pipe the /8 of ACLK to TA0CCR1.

Hello All,

  Looking at the block diagram of ADC12 on page 489 of  SLAU208H it would appear that the sample timer could use ADC12CLK to create the 8192hz sample clock. What wuld be the ideal ADC12SSELx clock to use.  The objective is to read A0 at a very accurate rate.  Wanting to run the CPU at 25Mhz, I have included an XT2 to source the DCO.  Is there any table or block diagram that is an overview of the clock distribution to on chip peripherals?

For a quick diagram of the clocks, there's page 87 of SLAU208H.  The UCS generates all of the clocks used in the system (with very few exceptions).

So ACLK, SMCLK, and MCLK are the 3 primary clocks.  Most peripherals can use any of these three clocks as you wish.  The fourth and final clock is MODCLK, which is special and usually available to very few peripherals, like the ADC.

Sourcing those clocks inside the UCS is a different matter.  There's XT1, XT2, VLO, REFO, and the DCO.  But no matter how you slice it, those sources end up available as ACLK, SMCLK, and MCLK.

What other purposes do you have for Timer A0?  Can you afford to dedicate it to ADC timing?  Do you use low power modes at all?  What frequency is ACLK?  You mentioned an 8192Hz sample rate, and you also mentioned ACLK/8, so is your ACLK 64kHz?  Do you have any other signals to sample besides A0?  Is the signal always present at A0?  And do you need your sampling time to be consistent (how long the sampling capacitor is integrated into the circuit to obtain the signal)?  Is it a DC signal?  Low impedence?

A fairly easy way to get a consistent conversion rate (so many samples per second) is to dedicate Timer A0 to the task and run it in UP mode.  Set CCR0 according to your conversion rate (number of ticks between conversions, minus 1).  Then setup CCR1 to drive OUT1 in Set/Reset mode.  Then every time the counter hits the CCR1 value (whatever you set it to, something less than CCR0), it will induce a conversion.

Also if you need precise control over your sampling time, you can put the ADC into extended sample mode and let OUT1 also control sampling timing.  Then your setting of CCR1 actually matters since its proximity to CCR0 would control the sampling time.

Jeff

The signal on A0 is always present.  It has an impedance of about 600 ohms. It has a bandwidth of about 4Khz.  Sorry about the /8 it should have been /4 if ACLK is 32khz. 

I will need to evaluate the use of TA0.  The 8192hz is not etched in stone but it will need to be above the hamming frequency for the bandwidth.  Would it make more sense to use the SMCLK or MCLK to clock the ADC and use the internal Sample timer to generate the sample clock?

Charles Olds said:

I am assuming that the reference to (internal) implies that it is an output of the TA0 but does not need to be on an output pin as the column "output pin number" implies.

Yep. The connection is internal and not routed through the output pin.

Charles Olds said:

Also what are you thoughts on configuring TA0 to pipe the /8 of ACLK to TA0CCR1.

You mean to use it as a trigger?

It most likely won't work. There's still the port pin input/output driver between them, so a signal applied to the port pin will not be routed to the CCRx compare output, it will only routed to the CCRx capture input. Which is a separate thing.

Charles Olds said:

I have included an XT2 to source the DCO

??? The DCO is the DCO and XT2 is XT2. Both are independent oscillators and can both be used to source one of the system clocks (MCLK, SMCLK, ACLK). But you cannot source DCO by XT2.

If you have SMCLK on 25MHz and select it as source for ADC12CLK, then for 8192Hz you'll need a timing of 25000000/8192 = 3051.75 clock ticks per conversion. The maximum SHT time is 1024 ticks. So if you divide SMCLK by 6 with ADC12DIVx (maximum ADC12CLK is 5MHz, bu t/5 gives an ugly result of 610), you'll get 508 ticks optimum. The closesst is ( SHT 512 +13 for the conversion and maybe +1 for sync)  = 526 ticks per conversion or 7921Hz. If that's okay for you, go this way.

Else you'll want to set upt the timerA or TimerB for a 8192Hz interval (e.g. by sourcing it with 25MHz and program CCR0 for 3052 ticks or whatever combination that gives you a cycle time of 1/8192 s and use the CCR1 (or on Timer B directly CCR0) as trigger for the sampling. Then SHT should be not used at all (using the 'duty cycle' of CCR1 to open and close the sample input, ADC12SHP is clear) or set to something that fits (when SHT12SHP is set). The ADC12CLK can then be adjusted to everything that's below 5MHz and above 8192*18 * ~150kHz. Depending on the SHT setting.  Even ADC12OSC is suitable in this case, since teh conversion is triggered by the timer and not dependent on ADC12CLK (whcih still controls the time required for doing the conversion itself, but not for the timing of the conversion start)

 

Charles Olds said:

Would it make more sense to use the SMCLK or MCLK to clock the ADC and use the internal Sample timer to generate the sample clock?

Yes, I think so, because 8192Hz isn't cast in stone, and because you apparently don't have any other analog inputs to worry about.  Just use the 25 MHz from MCLK or SMCLK and divide it down just as JMG suggests above.  The only trick will be to figure out exactly what sampling frequency you end up with!  It will be exactly consistent, but you'll have to study the User's Guide regarding continuous conversions to see what the timing is.  It's easy to be off by one or two counts of the ADC12CLK per sample, so watch out!

Use the other approach (dedicating Timer A0) only if you really need a specific sampling frequency.  The timer gives ultimate control over sampling time and conversion rate.

Jeff

 

Hello all,

  Sorry for the confusion on DCO and XT2.  What I meant to say was I had included an XT2 to source the FLLREFCLK for the DCO.  I chose to use TA0 as my clocking source for the ADC.  So far so good except for some rather strange behavior. Here is my configuration.

void ADC_Init(void)
{
  P6SEL |= 0x01;                                                                                        // Enable A/D channel A0
  ADC12CTL0 = ADC12REFON + ADC12ON ;                                    // Turn on REF,Turn on ADC12                                        
  ADC12CTL1 = ADC12SHS_1 + ADC12SSEL_2;                             // Use CCR1 for SAMPCON, Use MCLK for ADC12CLK
  ADC12IE = 0x01;                                                                                     // Enable ADC12IFG.0
  ADC12CTL0 |= ADC12ENC;                                                                 // Enable conversions
}

Notice the ADC12SHS_1.   According to my understanding this should select TA0.1 or TA0 CCR1 as the clocking source.  However no conversions occur.  If I include a line

ADC12CTL0 |= ADC12SC;                   // Start conversion

in main and again at the end of the ISR then I get data.   How can this be?

Here is the init code for TA0

void Timer_A0_Init(void)
{
  P1DIR |= BIT2;                                       // P1.2  output to check with scope
  P1SEL |= BIT2;                                      // P1.2  options select
  TA0CCTL1 = OUTMOD_7;                  // CCR1 reset/set
  TA0CCR0 = 497;                                 // Set TA0CCR0
  TA0CCR1 = 2;

  TA0CTL = TASSEL_2 + MC_1 + TACLR ;           // ACLK, count to TA0CCR0, clear TAR, /4
}

Even if  TA0 is set wrong shouldnt ADC12SC be ignored because i have selected TA0.1 with ADC12SHS_1?

I'm also surprised that ADC12SC still starts a conversion when it isn't configured as the trigger.  Maybe after you get things up and running the way you want you could come back to that little gem for curiosity's sake.

I think you want repeat single channel mode (CONSEQx = 10b, ADC12CTL1).

Also I think you want OUT1 to stay low for longer than just 2 clock ticks.  Make sure its low plenty long enough for the ADC12 to finish the conversion (>14 ADC12 clocks).  When OUT1 goes high, it starts sampling for the next conversion.  I'm not sure what happens if you ask it to start sampling for the next conversion while it's still converting the current sample.

Did you ever configure ADC12MCTL0?  This register controls which input channel (A0) and which reference to use for the conversion.

On MSP430F5529, the REF module is not under the control of the ADC12 by default.  Use the REF register to get it up and running to meet your needs.

What is the rate of your XT2 crystal?  A 4MHz crystal (or faster) could drive SMCLK directly without using the FLL and DCO.  Then you could clock TA0 and the ADC12 conversion clock from SMCLK, using the SMCLK dividers in the UCS as necessary and not the TA0 or ADC12 clock dividers (for best synchronization).  That would give you the best consistency in sampling rate.  If you are looking to use a DFT, you'll be happier if you get the timing just right.

Jeff

 

Jeff Tenney said:

I'm also surprised that ADC12SC still starts a conversion when it isn't configured as the trigger.

The use of ADC12SC is not as simple as it seems by reading the block diagram:
"When ADC12SC triggers a conversion, successive conversions can be triggered by the ADC12SC bit. When any other trigger source is used, ADC12ENC must be toggled between each conversion."
This indicates that ADC12SC is different from the other triggers and not just one of four. The state diagram also shows that ADC12S is handled differently. Maybe there's aglitch in the state machine.

Jeff Tenney said:

I'm not sure what happens if you ask it to start sampling for the next conversion while it's still converting the current sample.

IIRC, additional triggers during conversion are just ignored. That is in pulse mode. If you use he extended samplign mode, the OUT signal directly controls the S&H gate and in best case the conversion is not reliable.If, however, ADC12CLK is much higher than the timer clock (factor 7 for 12 bit conversion), 2 timer clock cycles are enough.

Jeff Tenney said:

On MSP430F5529, the REF module is not under the control of the ADC12 by default.  Use the REF register to get it up and running to meet your needs.

Or set the control bit that forwards control back to the ADC12 registers. (which IMHO should be the default state for code backwards compatibility, especially between 54xx and 54xxA)

Thank you all.

This is the most helpful and informative text I have read to date on using the TimerA CCR1 as the sample timer for the ADC12.

I wish that there were more answers like this and also more examples fro TI.

Mark