In trying to assure error free communication at 115200 baud for the USCI (UART mode), its not clear on options for clocking this device. We also need help in interpretation of UG table 15-4 and 15-5
The DCO table (pg 30 of the datasheet (SLAS735J)) shows +/-3% error across temperature. Added to the digital error shown in tables 15-4 and 15-5 of the user guide (SLAU144J) of -0.8/+0.6%, or 0/+1.6% (depending on over sample mode), we get an accumulated error of ~35% of a bit-time (start + 8 data + parity + stop). This may be OK for an ideally clocked device at the opposite end of the line. However it seems to imply two 'G2xx3 devices may have an issue (assuming they're off in opposite directions).
Three questions ...
1. For UG table 15-4 and 15-5 is that error expressed as "%-of-a-bit accumulated across the whole character"? (we *think* thats what the preceding paragraph is trying to state)
2. Is the ~35%-of-a-bit error across a character stated above correct?
3. If so, what is the solution for clocking this device in a way that allows UART to UART between two 'G2xx3? (HF mode not supported by LFXT1, and LF mode is not characterized (presumably not supported) for crystals other than 32768)
Thanks ... Jim