Hi Team,
Need your expertise on our customer's query. Posting on their behalf:
I am confronted with an interrupt conflict regarding ADC10 and Timer_A1. At first I built a voltage control loop with ADC10 for the voltage measurements. As found in an example the ADC10 works on its own clock and the CPU is switched OFF at ADC10-start in order to reduce noise. When the ADC10 is ready, the CPU is activated again. --- This loop works fine so far.
Secondly, I built a kind of time base with the timer_A1. With 16 Mhz DSO clock and divider 8 the timer clock is 2 MHz resp. 0.5 ms period. With Timer set to 20000 I got the expected 10 ms. The related ISR increments a long integer timeCount and with modulo 100 operation, the expected ONE SECOND could be observed at a port.
When running both together, the CPU got trapped when the timer interrupt occurred during the ADC10-CPUOFF time frame. This problem could be resolved successfully by masking the timer interrupt during ADC10 usage However, now the timer does not generate ONE SECOND any longer, because the masking hampers the timer interrupt very often ! Now the result is close to three seconds and this "time base" is unstable as well.
If you know any trick to resolve this problem, would really appreciate if you could share it. Otherwise, I guess, I need to generate an external "one second" signal and feed that into an unused port.
Thanks in advance!
Kind Regards,
Jejomar