Other Parts Discussed in Thread: MSP430FR5959
Using the MSP430FR5959 device, I have been having similar issues that others have commented on with regards to getting the external clock to work properly. I also seem to get different results depending on whether I build in debug vs release mode.
Below is my init code that is based on the example that Matt Calvo suggested:
PJSEL0 |= (BIT6 | BIT7); // For XT2 Only FRCTL0 = FRCTLPW | NWAITS_1; //Seems to be needed for FRAM based devices, but not in the example??? CSCTL0_H = CSKEY >> 8; // Unlock CS registers CSCTL1 = DCORSEL | DCOFSEL_4; // Set DCO to 16MHz (pg. 105) //CSCTL1 = DCOFSEL_6; CSCTL2 = SELS__HFXTCLK | SELM__HFXTCLK; //set SMCLK and MCLK to HFXTCLK (pg. 95) //SMCLK SEEMS TO RUN AT ~4MHz??? //CSCTL2 = SELS__DCOCLK | SELM__HFXTCLK; CSCTL3 = DIVS__1 | DIVM__1; // Set all dividers to 1 CSCTL4 |= HFXTDRIVE_3; //Set buffer drive to max CSCTL4 &= ~HFXTOFF; //Turn on HFXTCLK CSCTL4 |= HFXTBYPASS; //clk sig from oscillator (not crystal) CSCTL4 &= ~(HFFREQ0 | HFFREQ1); // 8MHz to 16MHz range CSCTL4 |= HFFREQ1; CSCTL5 &= ~(LFXTOFFG | HFXTOFFG); // Clear XT1 and XT2 fault flag (XT1 is undriven and will fault again) CSCTL0_H = 0; // Lock CS registers
CS_setExternalClockSource(0,16000000); //Is this needed?
If I change the CSCTL2 register to :
CSCTL2 = SELS__DCOCLK | SELM__HFXTCLK;
which runs the SMCLK off the DCO, it seems to work correctly in both debug and release modes. This seems like a pretty straight forward setup, so I'm confused why I am having so much trouble here.
Thanks!
-Ryan