This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Interrupt Processing: Status Register Behavior

One step in processing an interrupt acceptance is clearing the Status Register. Does this mean that the entire register is reset to its default state from a POR, or is only the GIE bit reset to its default state from a POR?

During return from an interrupt, one of the steps involves the Status Register, with all previous settings, popped from the stack. Does this mean the entire contents of the Status Register are returned to the state that it was in before the interrupt was accepted?

  • GIE controls whether IRQs are granted or not. Clearing this bit will prevent any IRQ but won’t clear any pending IRQ.
    When an interrupt is granted, the status register is saved on stack and the GIE bit is cleared, so the ISR cannot be interrupted (except by an NMI). The other status flags (zero, negative, overflow) are unaffected (well, for whatever it may be useful for to know the status of the main code at random position).
    On return from the ISR, the status register is restored form stack (including the set GIE bit) and further interrupts are granted. This is required because an interrupt can happen at any time and the interrupted code doesn’t know, so everything (all CPU registers and stack contents) must return to previous state. All global variables that are affected by an ISR need to be declared volatile.

    Since the LPM bits are too in the status register, they are also saved, cleared and later restored. If on restore, the KPM bits shall not be restored (to wake main form LPM), this can be done with a special pseudo-function (an intrinsic): __bic_SR_register_on_exit() (or bis_) which will alter the saved status register content on stack.
    On MSPs with MSP430X (20 bit) CPU core, the saved status register (which is 8 bit only, but saved as 16 bit) also contains the upper 4 bits of the return address. Which should not be touched, of course.