Questions are about using the SPI bus of the MSP430 (MSP430FR5989-EP) with 1 MSP430 as a Master and 2 additional MSP430 as a slave processor. The bus consists of 1 MSP430 as Master (SCLK, MOSI, MISO, SS1, and SS2), Slave 1 MSP430 (SCLK, MOSI, MISO, SS1), and Slave 2 (SCLK, MOSI, MISO, SS2). On each slave MSP430 the STE pin (P5.3 / UCB1STE) is used in input mode for slave select (SS1 or SS2 respectively). So Master is in 3-wire mode with GPIO chip select (slave select), Slaves are 4-wire slave mode using STE as input.
How do I know the STE pin as input works correctly for this particular MSP430 for 4-wire slave mode?
Since all devices are MSP430 uP on the bus, is there a best CKPH and CKPL (Clock Phase and Clock Polarity)? It seems like as long as they are all the same choice, it would not matter? Trying to use CKPH = 0 and CKPL = 0.
Is there a minimum time between the slave select line going low and when the MSP430 SPI state machine SCLK should starts (in terms of SCLK cycles maybe)? we have about 5uS. SCLK is currently 500kHz.
Note: The SPI comms work but then get errors. Ambient 24C to 25C. Can run the system 20C ambient in a temp chamber and it runs error free for days. a 4C delta temperature sounds like a timing error to me.