In developing for the TM4C I am using the SSI peripheral with the following settings: Freescale SPI with SPO=0 and SPH=0. With these settings the SSInFSS is toggled between each word of information on a continuous transfer. In looking over TI resources for this microcontroller I can find no minimum timing that SSInFSS is pulsed high between each word transmitted in a continuous transfer. I imagine this timing is somehow variable depending on system clock or the serial clock frequency. While it might be determined empirically for a given device I imagine there might be some variation between devices as well. So, is there at least some minimum timing or some specification on this parameter that would be adhered too for all manufactured parts of particular revisions?