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Part Number: TM4C129XNCZAD
The TM4C129X comes with strong suggestions for using SDRAM with and LCD and the EPI.
What features are required for achieving speeds necessary to drive a 800x480 color LCD? This LCD controller uses one byte to define pixels. It will need bytes at a rate half the pixel clock. Suppose the pixel clock is 30MHz, the LCD controller reads bytes at 15MHz.
Access time does not seem to matter since the EPI only runs at 60MHz. The max access time at those speeds is 17ns; slower than most SDRAM specs I see.
16 bit data vs 8 bit data is obviously twice the speed, but the EPI bus only has 31 signals, so there seems to be limits on how many data and address lines you get.
I have been told "the buffer access is limited the SDRAM burst mode is needed to provide enough data quick enough". Does Tivaware automatically make use of SDRAM burst, or is special configuration necessary? The TIvaWare Users guide only discusses burst in relation to Host Bus 16 mode.
Here is a timing diagram of SDRAM read timing using EPI. It is from page 833 of the datasheet. It shows reading 4 bytes in 7 EPI clock cycles.
Best Regards,Bob Crosby
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In reply to Bob Crosby:
Bob CrosbyIt shows reading 4 bytes in 7 EPI clock cycles.
Thanks for the drawing & explanation. I note: first the row data being presented, then the column data, a "NOP", and then 2, 16 bit (AD[15:0] MCU reads! The two 16 bit transfers read (32 bits, total) is the equivalent of 4 bytes (as you state) ... (also 32 bits) - is this understanding correct? Again thank you...
In reply to cb1_mobile:
In reply to Peter Borenstein:
I would suspect that resistor - in some (non-zero) resistance - provides a "better impedance (or level) match" between MCU's clock & RAM. (and such provision (saves) a pcb "hack" should the resistor be required - perhaps w/"certain" RAM chips.) When you write, "get 2 bytes (via 16 bit data I/O)" vendor's diagram shows, "back to back" such reads - which (I believe) yields "2 bytes, 2 times - thus 4 (total) bytes... (I asked for vendor confirmation as I do not use this MCU)
Here's a diagram from the same datasheet that shows a few more reads in "burst mode". AD[0:15] are changed to be driven in when data is on the bus. DQML and DQMH are signals which enable SDRAM output data pins.
cb1_mobileI would suspect that resistor - in some (non-zero) resistance - provides a "better impedance (or level) match" between MCU's clock & RAM. (and such provision (saves) a pcb "hack" should the resistor be required - perhaps w/"certain" RAM chips.)
Or the same footprint accommodates a chip w/o that input, or there was a layout limitation and physical jumper was used to avoid increasing the number of layers.
It's also possible that some chips need an inductive filter and the resistor is a placeholder, although that's an awfully small inductor.
Perhaps TI could enlighten?
In reply to Robert Adsett72:
It looks like this was added as a series termination resistor to avoid reflections on the clock line. In the end it looks like they did not need to add resistance, hence the value is zero Ohms. To answer the original question, is it required? In the case of the TI layout, no. However, it is not a bad idea to add it for a new layout, particularly if the CLK trace is long. It is easy to put in a zero Ohm resistor if no additional series resistance is needed.
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