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Part Number: TM4C1294KCPDT
It is taking unreasonable 400us for ADC converter cycles of 3 specific AINx channels, required for CADC to discharge between samples. CADC charge voltage is reluctant to go below some arbitrary threshold yet the ANIx input level reduces well below 1/4 VREFP amplitude <80mV. Hence 400us between triggering conversions allow for CADC to reluctantly discharge back to the arbitrary threshold first established, though not correct. The OPAMP output is consider settled in 9.6us to 0.5% of final value so the ADC is messing up in these conversions.
The OPAMP's are coupled 4.87k series resistance into single ended AINx inputs. The OPAMPs present <1nf load to each AINx input. Seemingly OPAMP should easily discharge CADC during push/pull cycles yet does not. What is going wrong CADC remains charged to arbitrary threshold yet FIFO's return 0V results after sampling stops? Conversion Interrupt occurs for the 3 AINx only during 400us triggering via GPTM one shot intervals. Seemingly plenty of time exists for CADC to discharge following AINx voltage changes as they fall below 1/4 VREFP. The application even forces the sample variable to 0x0 after each MIN/MAX evaluation each interrupt cycle. The variables and FIFO values are being drained, tested for under/over flow conditions. The application handling of FIFO results is not the problem as the hardware is misbehaving around CADC for what ever reason.
Why does CADC require so much time to discharge and what can be done in ADC configuration to correct behavior? The NSH set 0x4 or any other value has no effect to reduce the arbitrary CADC threshold, obviously floating FIFO value higher than AINx input voltage in this case.
Scope captures indicate CADC being charged only >400us settling:
In reply to BP101:
BP101Seemingly reverse current is flowing from the FIFO register into CADC keeping it charged to specific RC time constant of the PWM 80us periods.
No, that is not possible. The ADC is an analog macro done in 3V logic, the FIFO is all digital in the 1.2V domain. Your conclusion does not make sense from a chip design point of view.
Again, I suggest you not look inside the chip for the problem. If there were such a fundamental problem in the device, others would see it too. Verify your voltage at the pin and that you are sampling at the correct time. Check for FIFO overflow in your interrupt routine.
Best Regards,Bob Crosby
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In reply to Bob Crosby:
Bob CrosbyNo, that is not possible. The ADC is an analog macro done in 3V logic, the FIFO is all digital in the 1.2V domain. Your conclusion does not make sense from a chip design point of view
Ok yet CADC is simply not charge sharing center of 80us periods. The CADC values sampled remain very low FIFO read results. Yet if the trigger conversion is given 400µs between samples, CADC seems to share charge and acquisition the signal >40mV but never discharges again <40mV. So the signal can marginally be sampled but not at PWM0 trigger speeds. When we try to sample signal 20x gain CADC refuses to charge share <400us settling for signals >50-80mV, some where in that range. Long as the analog signal amplitude never exceeds say 80mV, CADC charge sharing cycles occur at PWM0 trigger speeds via the same SW.
Same OPAMP works correctly via Piccolo ADC TIDA-00909, perhaps something is not being disclosed in TM4C datasheet we need to know to make it work the same? Should customers have to reduce or alter amplifier gain in order for the TM4C ADC to properly charge share at PWM0 trigger speeds?
Bob CrosbyAgain, I suggest you not look inside the chip for the problem. If there were such a fundamental problem in the device, others would see it too.
Seemingly an assumption on your behalf that others are using the same TI amplifiers with TM4C1294 and never having this issue.
The samples align with reading of the FIFO results, verified via GPTM output pin. Yet the FIFO values never settle <400us or fall below 40mV once CADC has been charged to or beyond that valance level once the 20x gain signal becomes >80mV or so.
Below scope capture indicates samples via 400us Oneshot GPTM, versus PWM0 high speed triggering. Two samples @400us is all ADC can resolve via CADC charge share for the OPAMP signal reposted top of thread. PWM0 CH1 takes roughly 8 80us periods for CADC settle to 1/2 LSB. Should we be able to trigger sequencer via PWM0 to sample 20x gain analog signal? Seemingly there is an limitation TM4C can not sample (periodic) signals at PWM0 40us trigger speeds above a certain gain and properly acquisition the signal to 1/2 LSB. Such a restriction to amplifier gain allows error % to increase beyond mathematical predictability of SW to correctly determine any hardware changes made to reduce said gain. There in lies the paradox as to why PWM0 high speed triggering of sequencer samples breaks down in two distinct ways.
What is so different between Piccolo ADC TIDA-00909 as it properly acquisitions 10-25us periodic signal with same 20x amplifier gain? Might the sinusoidal attribute be an explanation for how CADC charge share behaves in 20x gain?
Interesting the Nyquist rate or sample conversion rate in this case 400us(2500Hz) is 10x slower than 1/2 the PWM frequency (12.5KHz) or 25KHz, Nyquist rate. The OPAMP bandwidth is 400KHz and ADC sample rate 2MSPS via 32Mhz ADC clock.
Seemingly the PWM clock is not synchronous with ADC clock by a factor of 10x and triggering precision conversions fail @40us(25KHz). Thus PWM center triggered conversion causes aliasing at twice the Nyquist rate sample component, (25KHz). Samples are seemingly off by several hundred electrical degrees in the high speed conversions. The question is why is the Nyquist sample rate needing to be slowed well below 25KHz in order to achieve precision signal acquisition?
I am unaware of how PWM clock rate (60MHz) relates to the ADC conversion clock rate (32MHz) in the Nyquist sample rate. Why is the correct Nyquist rate not possible to accurately acquisition signal CH1 created by PWM0 and converted by ADC0 clock sources? Obviously if your test example proves the ADC can sample 1mV then something else is not correct that cases CADC to remain charged >40mV and <80mV in 25KHz conversions of PWM triggers. We need basic peripheral clocking diagrams to be able to figure this issue out. TI has not provided necessary information in datasheet to accomplish this task in the field. Configuring ADC0, PWM0 60MHz did not make a difference and ADC0 clock 16Mhz (1MSPS) only slight difference in sample magnitude was noticed.
The Talk tab top paragraph adds another engineers view on the Wikipedia topic.
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