Need Tm4c1233h6pz GPIO pin configuring solution for my SSI communication

Hello Amit

As you  told if I wanna use GPIO_A6_SSI0FSS . It should be present in pinmap.h right? but the A6 pin was resrved for I2C pin in pinmap.h.

Does the pinmap.h macros allowed to do changes?

i.e.,

instead of #define GPIO_PA6_I2C1SCL        0x00001803, can I use #define GPIO_PA6_SSI0FSS        0x00001803 ?

Hello Amit

I changed in pinmap.h file from GPIO_PA6_I2C1SCL  to GPIO_PA6_SSI0FSS and commented GPIO_PA3_SSI0FSS. but still I am not able to use PA6 for SSI0FSS.Please look into the code I attached. I have attached write_command , write_data and SSD1306Init routines. 

#define DISPLAY_PINCFG_SSIFSS      GPIO_PA6_SSI0FSS

void SSD1306_SPI_Init(void)
{
  
    // Enable the peripherals used by this driver
    SysCtlPeripheralEnable(DISPLAY_SSI_PERIPH);
    SysCtlPeripheralEnable(DISPLAY_SSI_GPIO_PERIPH);
    SysCtlPeripheralEnable(DISPLAY_RST_GPIO_PERIPH);

    // Select the SSI function for the appropriate pins
    GPIOPinConfigure(DISPLAY_PINCFG_SSICLK);
    GPIOPinConfigure(DISPLAY_PINCFG_SSIFSS);
	
	  GPIOPinConfigure(DISPLAY_PINCFG_SSITX);

  	// Configure the pins for the SSI function
    GPIOPinTypeSSI(DISPLAY_SSI_PORT, DISPLAY_SSI_PINS);

    // Configure display control pins as GPIO output
    GPIOPinTypeGPIOOutput(DISPLAY_ENV_PORT, DISPLAY_ENV_PIN);
    GPIOPinTypeGPIOOutput(DISPLAY_D_C_PORT, DISPLAY_D_C_PIN);
		
		

    // Power off
    //GPIOPinWrite(DISPLAY_ENV_PORT, DISPLAY_ENV_PIN, 0);
   
    // Configure the SSI port
    SSIDisable(DISPLAY_SSI_BASE);
    SSIConfigSetExpClk(DISPLAY_SSI_BASE, SysCtlClockGet(),
                          SSI_FRF_MOTO_MODE_3, SSI_MODE_MASTER,
                          DISPLAY_SSI_CLOCK, 8);
    SSIEnable(DISPLAY_SSI_BASE);

    // Enable display power supply
    GPIOPinWrite(DISPLAY_ENV_PORT, DISPLAY_ENV_PIN, DISPLAY_ENV_PIN);
    // Send the initial configuration command bytes to the display
    SSD1306WriteCommand(g_ucDisplayInitCommands,
                             sizeof(g_ucDisplayInitCommands));
  			
  	//Set_Display_On_Off(0x01);
  	lcd_send_demo[0]=0x01;
  	SSD1306WriteCommand(lcd_send_demo, sizeof(lcd_send_demo));
		
	  Clr_Screen(0x00);
	 
}

/***************************write command************************************/
static void
SSD1306WriteCommand(const unsigned char *pcCmd, unsigned long ulCount)
{
    // Wait for any previous SSI operation to finish.
    while(SSIBusy(DISPLAY_SSI_BASE))
    {
    }

    //Set the D/C pin low to indicate command
    GPIOPinWrite(DISPLAY_D_C_PORT, DISPLAY_D_C_PIN, 0);
		
		//During every 8-bit transfer, making FSS as low
	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6,0);
	
    // Send all the command bytes to the display
    while(ulCount--)
    {
        SSIDataPut(DISPLAY_SSI_BASE, *pcCmd);
        pcCmd++;
    }
	
		//After every 8-bit transfer, making FSS as high to avoid data freeze
	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6, GPIO_PIN_6);//FSS=1
}

/*********************write data****************************************/

static void
SSD1306WriteData(const unsigned char *pcData, unsigned long ulCount)
{
    // Wait for any previous SSI operation to finish.
    while(SSIBusy(DISPLAY_SSI_BASE))
    {
    }

    // Set the D/C pin high to indicate data
    GPIOPinWrite(DISPLAY_D_C_PORT, DISPLAY_D_C_PIN, DISPLAY_D_C_PIN);
		
		//During every 8-bit transfer, making FSS as low
    GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6,0);

    // Send all the data bytes to the display
    while(ulCount--)
    {
        SSIDataPut(DISPLAY_SSI_BASE, *pcData);
        pcData++;
    }
		
		//After every 8-bit transfer, making FSS as high to avoid data freeze
    GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6,GPIO_PIN_6);
} 

Hello Amit

I used with this below steps as your suggestion, but its not working.

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_6, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU);

GPIODirModeSet(GPIO_PORTA_BASE, GPIO_PIN_6 , GPIO_DIR_MODE_OUT);

I have one more question, does SSI0 supports multi slave? i.e., using SSI0 I need to perform the below configuration for two SLAVES. If I can do this then how can I configure the pins as below. Coz I am facing problem with configuring PA6 as FSS. Kindly suggest me the proper working method I need to follow.

SLAVE1 : Clk = PA2,    FSS =  PA3,    Tx= PA5

SLAVE2 : Clk = PA2 , FSS = PA6 , Tx= PA7 

Looking forward for the answer

Thank you

#include "inc/tm4c1233h6pz.h"
#include "inc/hw_memmap.h"
#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_types.h"
#include "driverlib/gpio.h"
#include "driverlib/ssi.h"
#include "driverlib/sysctl.h"
#include "driverlib/rom.h"
#include "driverlib/pin_map.h"

#include "utils/uartstdio.h"
#include "utils/ustdlib.h"



//*****************************************************************************
//
// Defines the SSI and GPIO peripherals that are used for this display.
//
//*****************************************************************************
#define DISPLAY_SSI_PERIPH          SYSCTL_PERIPH_SSI0
#define DISPLAY_SSI_GPIO_PERIPH     SYSCTL_PERIPH_GPIOA
#define DISPLAY_RST_GPIO_PERIPH     SYSCTL_PERIPH_GPIOG

//*****************************************************************************
//
// Defines the GPIO pin configuration macros for the pins that are used for
// the SSI function.
//
//*****************************************************************************
#define DISPLAY_PINCFG_SSICLK       GPIO_PA2_SSI0CLK
#define DISPLAY_PINCFG_SSIFSS       GPIO_PA3_SSI0FSS
#define DISPLAY_PINCFG_SSITX        GPIO_PA5_SSI0TX

//*****************************************************************************
//
// Defines the port and pins for the SSI peripheral.
//
//*****************************************************************************
#define DISPLAY_SSI_PORT            GPIO_PORTA_BASE
#define DISPLAY_SSI_PINS            (GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5)

//*****************************************************************************
//
// Defines the port and pins for the display voltage enable signal.
//
//*****************************************************************************
#define DISPLAY_ENV_PORT            GPIO_PORTA_BASE
#define DISPLAY_ENV_PIN             GPIO_PIN_4

//*****************************************************************************
//
// Defines the port and pins for the display Data/Command (D/C) signal.
//
//*****************************************************************************
#define DISPLAY_D_C_PORT            GPIO_PORTA_BASE
#define DISPLAY_D_C_PIN             GPIO_PIN_7

//*****************************************************************************
//
// Defines the SSI peripheral used and the data speed.
//
//*****************************************************************************
#define DISPLAY_SSI_BASE            SSI0_BASE // SSI2
#define DISPLAY_SSI_CLOCK           1000000

#define XLevelL		0x00
#define XLevelH		0x10
#define XLevel		((XLevelH&0x0F)*16+XLevelL)

unsigned char Ascii_1[92][8]={		// Refer to "Times New Roman" Font Database...
						//   Basic Characters
	{0x00,0x00,0x00,0x00,0x5F,0x00,0x00,0x00}, //    33 '!'
	{0x00,0x00,0x00,0x07,0x00,0x07,0x00,0x00}, //    34 '"'
	{0x00,0x00,0x14,0x7F,0x14,0x7F,0x14,0x00}, //    35 '#'
	{0x00,0x00,0x24,0x2A,0x7F,0x2A,0x12,0x00}, //    36 '$'
	{0x00,0x02,0x45,0x32,0x08,0x26,0x51,0x20}, //    37 '%'
	{0x00,0x32,0x4D,0x49,0x51,0x20,0x50,0x00}, //    38 '&'
	{0x00,0x00,0x00,0x04,0x03,0x01,0x00,0x00}, //    39 '''
	{0x00,0x00,0x00,0x1C,0x22,0x41,0x00,0x00}, //    40 '('
	{0x00,0x00,0x00,0x41,0x22,0x1C,0x00,0x00}, //    41 ')'
	{0x00,0x04,0x44,0x28,0x1F,0x28,0x44,0x04}, //    42 '*'
	{0x00,0x08,0x08,0x08,0x7F,0x08,0x08,0x08}, //    43 '+'
	{0x00,0x00,0x80,0x60,0x20,0x00,0x00,0x00}, //    44 ','
	{0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08}, //    45 '-'
	{0x00,0x00,0x00,0x60,0x60,0x00,0x00,0x00}, //    46 '.'
	{0x00,0x00,0xC0,0x30,0x0C,0x03,0x00,0x00}, //    47 '/'
  {0x00,0x3E,0x41,0x41,0x41,0x41,0x3E,0x00}, //    48 '0'
	{0x00,0x00,0x00,0x02,0x7F,0x00,0x00,0x00}, //    49 '1'
	{0x00,0x42,0x61,0x51,0x49,0x45,0x42,0x00}, //    50 '2'
	{0x00,0x22,0x41,0x49,0x49,0x49,0x36,0x00}, //    51 '3'
	{0x00,0x10,0x18,0x14,0x52,0x7F,0x50,0x00}, //    52 '4'
	{0x00,0x4F,0x49,0x49,0x49,0x49,0x31,0x00}, //    53 '5'
	{0x00,0x3C,0x4A,0x49,0x49,0x49,0x30,0x00}, //    54 '6'
	{0x00,0x01,0x01,0x41,0x31,0x0D,0x03,0x00}, //    55 '7'
	{0x00,0x36,0x49,0x49,0x49,0x49,0x36,0x00}, //    56 '8'
	{0x00,0x06,0x49,0x49,0x49,0x29,0x1E,0x00}, //    57 '9'
	{0x00,0x00,0x00,0x66,0x66,0x00,0x00,0x00}, //    58 ':'
	{0x00,0x00,0x80,0x66,0x26,0x00,0x00,0x00}, //    59 ';'
	{0x00,0x08,0x08,0x14,0x14,0x22,0x22,0x00}, //    60 '<'
	{0x00,0x24,0x24,0x24,0x24,0x24,0x24,0x24}, //    61 '='
	{0x00,0x22,0x22,0x14,0x14,0x08,0x08,0x00}, //    62 '>'
	{0x00,0x00,0x02,0x01,0x51,0x09,0x06,0x00}, //    63 '?'
	{0x00,0x1C,0x22,0x49,0x55,0x49,0x12,0x0C}, //    64 '@'
	{0x00,0x40,0x70,0x1C,0x17,0x1C,0x70,0x40}, //    65 'A'
	{0x00,0x7F,0x49,0x49,0x49,0x49,0x49,0x36}, //    66 'B'
	{0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x22}, //    67 'C'
	{0x00,0x7F,0x41,0x41,0x41,0x41,0x22,0x1C}, //    68 'D'
	{0x00,0x7F,0x49,0x49,0x49,0x49,0x41,0x41}, //    69 'E'
	{0x00,0x7F,0x09,0x09,0x09,0x09,0x01,0x01}, //    70 'F'
	{0x00,0x1C,0x22,0x41,0x41,0x49,0x49,0x7A}, //    71 'G'
	{0x00,0x7F,0x08,0x08,0x08,0x08,0x08,0x7F}, //    72 'H'
	{0x00,0x00,0x41,0x41,0x7F,0x41,0x41,0x00}, //    73 'I'
	{0x00,0x30,0x40,0x40,0x41,0x41,0x3F,0x00}, //    74 'J'
	{0x00,0x7F,0x08,0x08,0x14,0x22,0x41,0x00}, //    75 'K'
	{0x00,0x7F,0x40,0x40,0x40,0x40,0x40,0x00}, //    76 'L'
	{0x00,0x7F,0x02,0x04,0x08,0x04,0x02,0x7F}, //    77 'M'
	{0x00,0x7F,0x02,0x04,0x08,0x10,0x20,0x7F}, //    78 'N'
	{0x00,0x1C,0x22,0x41,0x41,0x41,0x22,0x1C}, //    79 'O'
	{0x00,0x7F,0x09,0x09,0x09,0x09,0x09,0x06}, //    80 'P'
	{0x00,0x1C,0x22,0x41,0x41,0xC1,0xA2,0x9C}, //    81 'Q'
	{0x00,0x7F,0x09,0x09,0x09,0x19,0x29,0x46}, //    82 'R'
	{0x00,0x26,0x49,0x49,0x49,0x49,0x49,0x32}, //    83 'S'
	{0x00,0x01,0x01,0x01,0x7F,0x01,0x01,0x01}, //    84 'T'
	{0x00,0x3F,0x40,0x40,0x40,0x40,0x40,0x3F}, //    85 'U'
	{0x00,0x01,0x07,0x18,0x60,0x18,0x07,0x01}, //    86 'V'
	{0x00,0x7F,0x20,0x10,0x08,0x10,0x20,0x7F}, //    87 'W'
	{0x00,0x41,0x22,0x14,0x08,0x14,0x22,0x41}, //    88 'X'
	{0x00,0x01,0x02,0x04,0x78,0x04,0x02,0x01}, //    89 'Y'
	{0x00,0x41,0x61,0x51,0x49,0x45,0x43,0x41}, //    90 'Z'
	{0x00,0x00,0x00,0x00,0x7F,0x41,0x41,0x00}, //    91 '['
	{0x00,0x00,0x03,0x0C,0x30,0xC0,0x00,0x00}, //    92 '\'
	{0x00,0x00,0x41,0x41,0x7F,0x00,0x00,0x00}, //    93 ']'
	{0x00,0x00,0x04,0x02,0x01,0x02,0x04,0x00}, //    94 '^'
	{0x00,0x80,0x80,0x80,0x80,0x80,0x80,0x80}, //    95 '_'
	{0x00,0x00,0x00,0x01,0x03,0x04,0x00,0x00}, //    96 '`'
	{0x00,0x38,0x44,0x44,0x44,0x44,0x24,0x7C}, //    97 'a'
	{0x00,0x7F,0x44,0x44,0x44,0x44,0x44,0x38}, //    98 'b'
	{0x00,0x38,0x44,0x44,0x44,0x44,0x44,0x00}, //    99 'c'
	{0x00,0x38,0x44,0x44,0x44,0x44,0x44,0x7F}, //   100 'd'
	{0x00,0x38,0x54,0x54,0x54,0x54,0x54,0x18}, //   101 'e'
	{0x00,0x04,0x7E,0x05,0x05,0x01,0x01,0x00}, //   102 'f'
	{0x00,0x18,0xA4,0xA4,0xA4,0xA4,0xA4,0x7C}, //   103 'g'
	{0x00,0x7F,0x04,0x04,0x04,0x04,0x04,0x78}, //   104 'h'
	{0x00,0x00,0x44,0x44,0x7D,0x40,0x40,0x00}, //   105 'i'
	{0x00,0x00,0x80,0x84,0x84,0x84,0x7D,0x00}, //   106 'j'
	{0x00,0x7F,0x10,0x10,0x28,0x44,0x44,0x00}, //   107 'k'
	{0x00,0x00,0x00,0x41,0x7F,0x40,0x00,0x00}, //   108 'l'
	{0x00,0x7C,0x04,0x04,0x38,0x04,0x04,0x78}, //   109 'm'
	{0x00,0x7C,0x08,0x04,0x04,0x04,0x04,0x78}, //   110 'n'
	{0x00,0x38,0x44,0x44,0x44,0x44,0x44,0x38}, //   111 'o'
	{0x00,0xFC,0x44,0x44,0x44,0x44,0x44,0x38}, //   112 'p'
	{0x00,0x38,0x44,0x44,0x44,0x44,0x44,0xFC}, //   113 'q'
	{0x00,0x00,0x7C,0x08,0x04,0x04,0x04,0x00}, //   114 'r'
	{0x00,0x48,0x54,0x54,0x54,0x54,0x24,0x00}, //   115 's'
	{0x00,0x04,0x04,0x3F,0x44,0x44,0x44,0x00}, //   116 't'
	{0x00,0x3C,0x40,0x40,0x40,0x40,0x20,0x7C}, //   117 'u'
	{0x00,0x04,0x0C,0x30,0x40,0x30,0x0C,0x04}, //   118 'v'
	{0x00,0x3C,0x40,0x40,0x38,0x40,0x40,0x3C}, //   119 'w'
	{0x00,0x44,0x44,0x28,0x10,0x28,0x44,0x44}, //   120 'x'
	{0x00,0x1C,0xA0,0xA0,0xA0,0xA0,0x7C,0x00}, //   121 'y'
	{0x00,0x44,0x64,0x54,0x54,0x4C,0x44,0x00}, //   122 'z'
	{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}		//   ( 91)    - 0x00A0 No-Break Space
};
												

//*****************************************************************************
//
// An array that holds a set of commands that are sent to the display when
// it is initialized.
//
//*****************************************************************************
static
unsigned char g_ucDisplayInitCommands[] =
{
    //0xAE,                    // display off
    0xD5, 0x80,                // master control current 7/16
    0xA8, 0x3F,                // contrast A control
    0xD3, 0x0,                 // contrast B control
    (0x40 | 0x0), 0x8D,        // contrast C control
    0x14, 0x20,                // remap and data format - use 8-bit color mode
    0x02, (0xA0 | 0x1),        // Vpa
    0xC8, 0xDA,                // Vpb
    0x12, 0x81,                // Vpc
    //0xAD, 0x8E,              // internal Vp, external supply
    0xCF, 0xd9,                // rectangle fill enabled
    0xF1, 0xDB,                // display on
	0x40, 0xA4,
	0xA6, 0xAF,
	0XA6
};

static unsigned char lcd_send_demo[1];
unsigned char demo_screen=0;

unsigned char Fill_RAM_Space=0x00;


//******************************SSD1306WriteCommand*****************************


static void
SSD1306WriteCommand(const unsigned char *pcCmd, unsigned long ulCount)
{
    // Wait for any previous SSI operation to finish.
    while(ROM_SSIBusy(DISPLAY_SSI_BASE))
    {
    }

    //Set the D/C pin low to indicate command
    ROM_GPIOPinWrite(DISPLAY_D_C_PORT, DISPLAY_D_C_PIN, 0);
	  ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3,0);//cs=0
	
    // Send all the command bytes to the display
    while(ulCount--)
    {
        ROM_SSIDataPut(DISPLAY_SSI_BASE, *pcCmd);
        pcCmd++;
    }
	
	  ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);//cs=1
}

//*******************************SSD1306WriteData****************************


static void
SSD1306WriteData(const unsigned char *pcData, unsigned long ulCount)
{
    // Wait for any previous SSI operation to finish.
    while(ROM_SSIBusy(DISPLAY_SSI_BASE))
    {
    }

    // Set the D/C pin high to indicate data
    ROM_GPIOPinWrite(DISPLAY_D_C_PORT, DISPLAY_D_C_PIN, DISPLAY_D_C_PIN);
    ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3,0);//cs=0

    // Send all the data bytes to the display
    while(ulCount--)
    {
        ROM_SSIDataPut(DISPLAY_SSI_BASE, *pcData);
        pcData++;
    }
		
    ROM_GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3,GPIO_PIN_3);//cs=1
}

//************************Set_Start_Column*************************

void Set_Start_Column(unsigned char Start_Column)
{
	// Set Lower Column Start Address for Page Addressing Mode
	lcd_send_demo[0]=(0x00+Start_Column%16);
	SSD1306WriteCommand(lcd_send_demo, sizeof(lcd_send_demo));	
						
	// Set Higher Column Start Address for Page Addressing Mode
	lcd_send_demo[0]=(0x10+Start_Column/16);
	SSD1306WriteCommand(lcd_send_demo, sizeof(lcd_send_demo));
					
}

//***************************Set_Start_Page*******************************

void Set_Start_Page(unsigned char Start_Page)
{
	// Set Page Start Address for Page Addressing Mode
	lcd_send_demo[0]= (0xB0|Start_Page);
	SSD1306WriteCommand(lcd_send_demo, sizeof(lcd_send_demo));
						
}


//***************************Clr_Screen***********************************


void Clr_Screen(unsigned char Data)
{
unsigned char i,j;

	for(i=0;i<8;i++)
	{
		if(Fill_RAM_Space == 0x01)
		{
			i=7;
		}
		Set_Start_Page(i);
		Set_Start_Column(0x00);

		for(j=0;j<128;j++)
		{
			lcd_send_demo[0] = Data;
			SSD1306WriteData(lcd_send_demo, sizeof(lcd_send_demo));
		}
	}
}

//*******************************Display_Character******************************

void 
Display_Character(unsigned char Character_Case_Select, unsigned char Ascii_Value,
                       unsigned char Page_Addrs, unsigned char Column_Addrs)
{
    unsigned char *Src_Pointer;
    unsigned char i;

	switch(Character_Case_Select)
	{
		case 1:
		Src_Pointer=&Ascii_1[(Ascii_Value-33)][0];
			break;
		case 2:
		Src_Pointer=&Ascii_1[(Ascii_Value-1)][0];
			break;
	}
	Set_Start_Page(Page_Addrs);
	Set_Start_Column(Column_Addrs);

	for(i=0;i<8;i++)
	{
		lcd_send_demo[0]= (*Src_Pointer);
		SSD1306WriteData(lcd_send_demo, sizeof(lcd_send_demo));
		Src_Pointer++;
	}
		lcd_send_demo[0]= 0x00;
	SSD1306WriteData(lcd_send_demo, sizeof(lcd_send_demo));
}

//******************************Display_String***********************


void Display_String(unsigned char Character_type, unsigned char *Data_Pointer, 
                    unsigned char Page_Addrs, unsigned char Column_Addrs)
{
    unsigned char *Src_Pointer;

	Src_Pointer=Data_Pointer;
	//Must be written first before the string start...
	Display_Character(1,91,Page_Addrs,Column_Addrs);			
						

	while(1)
	{
		Display_Character(Character_type,*Src_Pointer,Page_Addrs,Column_Addrs);
		Src_Pointer++;
		Column_Addrs+=8;
		if(*Src_Pointer == 0) 
		break;
	}
}

//****************************SSD1306_SPI_Init***************************

void SSD1306_SPI_Init(void)
{
  
    // Enable the peripherals used by this driver
    ROM_SysCtlPeripheralEnable(DISPLAY_SSI_PERIPH);
    ROM_SysCtlPeripheralEnable(DISPLAY_SSI_GPIO_PERIPH);
    ROM_SysCtlPeripheralEnable(DISPLAY_RST_GPIO_PERIPH);

    // Select the SSI function for the appropriate pins
    ROM_GPIOPinConfigure(DISPLAY_PINCFG_SSICLK);
    GPIOPinConfigure(DISPLAY_PINCFG_SSIFSS);
	

	
	  ROM_GPIOPinConfigure(DISPLAY_PINCFG_SSITX);

  	// Configure the pins for the SSI function
    ROM_GPIOPinTypeSSI(DISPLAY_SSI_PORT, DISPLAY_SSI_PINS);

    // Configure display control pins as GPIO output
  
    ROM_GPIOPinTypeGPIOOutput(DISPLAY_ENV_PORT, DISPLAY_ENV_PIN);
    ROM_GPIOPinTypeGPIOOutput(DISPLAY_D_C_PORT, DISPLAY_D_C_PIN);
		
		 //  power off
      ROM_GPIOPinWrite(DISPLAY_ENV_PORT, DISPLAY_ENV_PIN, 0);
   
   
    // Configure the SSI port
    ROM_SSIDisable(DISPLAY_SSI_BASE);
    ROM_SSIConfigSetExpClk(DISPLAY_SSI_BASE, ROM_SysCtlClockGet(),
                          SSI_FRF_MOTO_MODE_3, SSI_MODE_MASTER,
                          DISPLAY_SSI_CLOCK, 8);
    ROM_SSIEnable(DISPLAY_SSI_BASE);

     // Enable display power supply
    ROM_GPIOPinWrite(DISPLAY_ENV_PORT, DISPLAY_ENV_PIN, DISPLAY_ENV_PIN);

    // Send the initial configuration command bytes to the display
    SSD1306WriteCommand(g_ucDisplayInitCommands,
                             sizeof(g_ucDisplayInitCommands));
	Clr_Screen(0x00);
		
	//Set_Display_On_Off(0x01);
	lcd_send_demo[0]=0x01;
	SSD1306WriteCommand(lcd_send_demo, sizeof(lcd_send_demo));
		
	Clr_Screen(0x00);
	
 
}

//**********************main******************************************

int main()
{
   	 SSD1306_SPI_Init();
     Display_String(1,"hi",0x00,XLevel+0x25);

}
	

Sorry I dint informed about the slave module. I am using SSD 1306 controller based OLED from Sunrom (model number = 1258)

Hello Amit

As your inputs I could able to Configure PA6 as my SSIFSS pin . Thanks for the same.

My question now is .. whether I need to handle RST pin in any Condition of my data transfer? At what situations I need to handle my RESET pin during SSI transaction? 

My understanding is before GPIO pin configuration , we need to do reset.

Thank you

Okay.Got it. you mean to say that , if I want to switch from SSI0 to SSI1 (or any other SSI modules) ... I need to do RESET before using the specified SSI module. Am I right?

One more question Amit.

Why in tm4c123gxl datasheet the SSI1 module is provided with 2 Clks port pins( i.e., PF2 and PD0), 2 FSS port pins( i.e., PF3 and PD1) , 2 Rx port pins( i.e.,PF0 and PD2), and 2 Tx Port pins( i.e., PF1 and PD3) . Does it says, that it can support simultaneous 2 slaves for the master ( tm4c123gxl).....? OR for any other reason.. where I am failing to understand?

Hello Amit

As you suggested above simple changes doesn't matter much I feel. Because GPIOPinTypeGPIOOutput  function inernally uses GPIOPadConfigSet and GPIODirModeSet functions. But I tried as per your suggestion, The OLED display is not happening with GPIO A6 as SSI_FSS.  

Also I came across one more thing in terms of registers used in GPIOPadConfigSet function. specifically I am speaking about GPIO Pheripheral configuration register(GPIO_O_PC).  I think this register is not applicable for tm4c123gxl. Then how the GPIO pins can be configured as SSI pheripheral pin? As per my understanding what ever Functions I am trying to use, is not going to work.!!! 

  OR

The configuration can be done without the GPIO_O_PC register? If YES, HOW it works internally? 

Regards

Nethra

Dear Amit

As you told, I am unlocking the gpio PF0 using the below function.Is it what I am using is correct or anything I need to take care?

void Configure (void)
{

HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
HWREG(GPIO_PORTF_BASE + GPIO_O_CR) |= 0x01;
HWREG(GPIO_PORTF_BASE + GPIO_O_AFSEL) |= 0x400;
HWREG(GPIO_PORTF_BASE + GPIO_O_DEN) |= 0x01;
HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = 0;

}

void SPI_Init(void)
{

Configure(); // unlocking PF0

// Enable the peripherals used by this driver
SysCtlPeripheralEnable(DISPLAY_SSI_PERIPH);  // SSI1 enable
SysCtlPeripheralEnable(DISPLAY_SSI_GPIO_PERIPH_PA_EN); // Port A enable for OLED slave D/C pin
SysCtlPeripheralEnable(DISPLAY_SSI_GPIO_PERIPH); // port D enable for SSI_clk, SSI_FSS, SSI_Tx
SysCtlPeripheralEnable(DISPLAY_RST_GPIO_PERIPH); // Reset pin enable

// Select the SSI function for the appropriate pins
GPIOPinConfigure(DISPLAY_PINCFG_SSICLK);  // PD0
GPIOPinConfigure(DISPLAY_PINCFG_SSIFSS);  // PD1

GPIOPinConfigure(DISPLAY_PINCFG_SSITX);    // PD3

GPIOPinConfigure(DISPLAY_PINCFG_SSIRX);   //PD2

// Configure the pins for the SSI function
GPIOPinTypeSSI(DISPLAY_SSI_PORT, DISPLAY_SSI_PINS); // Configure PD0, PD1, PD3

....

....

...

}

But.,I dint understood, why I should unlock PF0 pin? When I am trying to communicate with PORT_D pins( PD0, PD1, PD2, PD3). !!!

Dear Amit

I apologies for my poor english. 
I am trying out all the slave modules communication. i.e., SSI0 , SSI1 , SSI2 and SSI3 for tm4c123gxl.
I could able to achieve the communication with your help for SSI0 ( port_A set), SSI1( port_F set), SSI2( port_B set) .
But I could not able to do with SSI1(port_D set) and SSI3(port_D set). I actually mean this above statements in my last post.

The SSI1 (port_F set) worked for me without PF0 unlocking, because PF0 corresponds to SSI1_Rx, and I am not using SSI1_Rx pin, So.

Similarly I am not using SSI1_Rx for SSI1(port_D set) , So, as per my understanding unlocking PF0 is not required for my application for communication of SSI1 using port_D set. Am I correct !

So attached the code which uses the port_D set of SSI1 and in the code I have not tried unlocking the PF0 pin.

Also accordingly I am trying out the debugging as you told.

Thank you.

Dear Amit

No need to apologies. Thanks for the confirmation for not unlocking the pin PF0 as I dont use SSI1_Rx pin.

Okay, Thanks also for clarification regarding the PD0 and PD1 pins. I will try with SSI1(port_D set  ) and SSI3 shortly.

Very Good job/Support Amit.

Regards

Nethra

Dear Amit

Boss, I removed R9 and R10 0 Ohms resisters but no output from PortD. Is there anything else I need to take care for SSI1 port D configuration??????????????????

Amit., Do you have any Specificdocumentation , which says how to handle all these SSI ports and pins clearly other than user guide and datasheet. If so, It will be of great use for me.

Sure, Okay . Thank you.

Hello Amit

Hope my question might be so silly. But still asking.

I was trying to toggle the PortD SSI pins( i.e., PD0, PD1, PD3 ) to confirm for the pins working condition. Pin PD0 and PD1 is toggling fine., but when I was checking for PD3 I came across two scenarios...

1) . With one launchpad Instead of giving HIGH( 3.3V ) , the pin showing low state only. Looks like pin might have went bad.

2) . With the second launchpad Instead of giving 3.3V , the PD3 pin was showing 2.0V . It remains the same, though I make the pin as low. What this specifies? Is this a tristate condition the pin is going into.?

Note: I am trying this toggling method of pin checking BY REMOVING THE SHORT B/W PortD and PortB pins using R9 and R10 resistors.

Thank you.

Regards

Nethra