TM4C129x SPI Receive Time-Out Time

The Tiva TM4C129x Register 7 QSSI Raw Interrupt Status is being read for Receive Time-Out (RTRIS) and FIFO Overflow (RORRIS) errors for SPI Communications. The Receive Time-Out (RTRIS) is occurring occasionally.

It appears that the Tiva TM4C129DNCZAD Microcontroller DATA SHEET (SPMS440B) does not indicate what the SPI Receive Time-Out time is or how to change it.

QUESTIONS:

1. What is the Receive Time-Out time?
2. Is it possible to increase the Receive Time-Out time?

Thank you for your time and efforts,

Tim