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I'm looking at the Interfacing SDRAM Memory on High Performance Microcontrollers (TIDM-TM4C129XSDRAM) design guide, and I don't understand why the RFSH value is set as it is.
RFSH is set to a value of 1024 at line 435 of the dktm4c129_sdram_performance_example.c file in the provided software example, with a call to EPIConfigDRAMSet():
EPIConfigSDRAMSet(EPI0_BASE, (ui32Freq | EPI_SDRAM_FULL_POWER | EPI_SDRAM_SIZE_512MBIT), 1024);
The system clock frequency is 120 MHz and the EPI clock frequency is set to 60 MHz. The EPI is being used in SDRAM mode.
According to the datasheet for the TM4C129XNCZAD part (sect 220.127.116.11), the refresh value should be calculated as:
RFSH = (t Refresh_us / number_rows) / ext_clock_period
t Refresh_us = the refresh period for the SDRAM in us.
number_rows = the number of rows in each SDRAM bank (either 4096 or 8192).
ext_clock_period = the period of a single EPI clock period in μs.
The example provided in the datasheet shows how to calculate for a 64 ms refresh period (64000 μs) with a 4096 row part with an external clock speed of 50 MHz (0.02 μs period):
RFSH = (64000 / 4096) / 0.02 = 15.625 μs / 0.02 μs = 781.25
You then pick a value LESS than this to provide some margin.
In the design guide, the SDRAM part referenced is an ISSI 512Mbit SDRAM Memory. The datasheet for this part states that it has "8K refresh cycles every 64 ms." It think that this means that it has a 64 ms refresh period with 8192 rows. With a 60 MHz EPI clock (0.0167 μs period), the calculation becomes:
RFSH = (64000 / 8192) / 0.0167 = 7.8125 μs / 0.0167 = 467.81
How can a value of 1024 be okay in this case? It's much higher that then the calculated RFSH value.
Even if the part actually had only 4096 rows the calculation is:
RFSH = (64000 / 4096) / 0.0167 = 15.625 μs / 0.0167 = 935.63
For which 1024 still wouldn't be acceptable.
Is there something I'm missing or is the example code not correct?
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