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TM4C1294NCPDT: errata SYSCTL#22 questions

Errol Leon6
Expert 5830 points
Part Number: TM4C1294NCPDT

Hello,

 

My customer has a few questions regarding errata SYSCTL#22 for the Tiva TM4C1294NCPDT.

 

The errata description is:

 

When generating system clock from the PLL, the user programs the system control register bits RSCLKCFG.PSYSDIV to divide the PLL output. This register value may not be loaded into the physical divider causing the system clock to be divided by 2. This condition will cause the system clock to be out of specification.

 

1)    The customer believes they might be experiencing this issue on a couple of boards when powering on at -10C.  These same boards operate correctly at higher temperatures, and other boards operate correctly across the entire temperature range.  Applying the workaround appears to fix the boards that exhibited the problem at -10C, but they’d like to have higher confidence that they are addressing the real issue and that it isn’t just intermittent.  Can you provide any additional information on what conditions can cause the register to not be loaded as described in the errata?

2)      Not sure if we understand the errata fully.  The description sounds like the RSCLKCFG.PSYSDIV register can errantly be set to divide by 2 when you write the register with a value to divide by something other than 2.  That would lead us to believe that RSCLKCFG.PSYSDIV should always be set to divide by 2 to ensure it divides as you expect.  However, the code changes in the workaround set RSCLKCFG.PSYSDIV to different values.  The changes in the workaround does, however, always set PLLFREQ1.Q to divide by 2 (old code divided by 1).  Is the description wrong and it is really PLLFREQ1.Q that may not be loaded correctly?

3)      The workaround runs the VCO frequency at either 160MHz or 240Mhz instead of 320MHz or 480MHz.  This means one cannot simultaneously run the CPU at 120MHz and the ADC clock at 32MHz for 2 Msps with the workaround.  Correct?

4)    We’d like to run 25MHz MOSC, 480MHz VCO, 32MHz ADC clock, and 120 MHz CPU/SYSCLK.  Are either of the following valid ways to do this while working around errata SYSCTL#22:

a.     Set PLLFREQ0.MINT to multiply by 192, PLLFREQ1.Q to divide by 2, PLLFREQ1.N to divide by 5, ADCC.CLKDIV to divide by 15, and RSCLKCFG.PSYSDIV to divide by 4.

 

OR

 

b.       Set PLLFREQ0.MINT to multiply by 96, PLLFREQ1.Q to divide by 1, PLLFREQ1.N to divide by 5, ADCC.CLKDIV to divide by 15, and RSCLKCFG.PSYSDIV to divide by 4.  But loop and rewrite PLLFREQ1 as needed until PLLFREQ1.Q reads back correctly, and loop rewriting RSCLKCFG.PSYSDIV until it reads back correctly.  Also, delay switching from PIOSC to the PLL clock until after RSCLKCFG.PSYSDIV has been read back correctly.

 

Any additional insight into SYSCTL#22 would be helpful and appreciated.  Thank you in advance for your support!

 

Thanks!

Errol Leon

Texas Instruments

Field Applications Engineer

  • 0
    TI__Guru 72500 points

    Errol Leon6 said:
    Can you provide any additional information on what conditions can cause the register to not be loaded as described in the errata?

    Not really. The root cause of the issue is that there are two registers that provide the PSYDIV count preload. The one that you write and read, and an internal shadow register. To avoid disrupting the clock signal when writing the visible PSYDIV bits if they are not changed, the shadow register is not reloaded unless there is a change in the visible register. When the two registers power-up in different states the write to the visible register might not propagate to the shadow register leaving it in a divide by 2. The workaround was chosen such that the PLL was set to 240MHz and a divide by 2 does not cause the system clock to exceed the maximum frequency of 120MHz.

    By design register bits power up randomly. These bits are clocked by the PLL instead of the system clock and therefore are not always properly reset. The power on state of any such bit is a function of process (each bit in each device is slightly different), voltage and temperature. The fact that you have some devices that fail only at cold temperature is consistent with this problem, but each device will behave uniquely.

    Errol Leon6 said:
    Is the description wrong and it is really PLLFREQ1.Q that may not be loaded correctly?

    It is the PSYDIV bits. Hopefully the description above helps to explain.

    Errol Leon6 said:
    This means one cannot simultaneously run the CPU at 120MHz and the ADC clock at 32MHz for 2 Msps with the workaround.  Correct?

    Yes, with the current workaround that is correct.

    Errol Leon6 said:
    Are either of the following valid ways to do this while working around errata SYSCTL#22:

    No because both methods rely upon proper reads and writes of PSYDIV. If they must have the CPU at 120MHz and the ADC at 32Mhz, They can try using the given workaround (PLL=240MHz, SYSCLK=120MHz), then changing the PSYDIV to 3 (divide by 4) and verify (compare against PIOSC or crystal) that SYSCLK is now 60MHz. Then switch back to PIOSC and initialize the PLL to 480MHz. This should work because you have successfully synchronized the visible PSYDIV bits with their shadow counterparts.