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TM4C1294KCPDT: Sequencer step noise

Guru 47685 points

Replies: 4

Views: 171

Part Number: TM4C1294KCPDT

ADC1 Sequencer 1 AIN16 (step 0) FIFO rolls mixed hex values compared to very quite AIN9 (step 1), both have sensor LM94022.  Reversing sequencer steps moves the noise to AIN9 step 0 , proving AIN16 trace and sensor are not the problem. Multiple MCU have all had the very same issue step 0 AINx must have pull down 3.9k - 4.87k versus any added decoupling capacitance order to reduce SNR on step 0.  

Why is ADC1 sequencer 1 step 0 reacting to internal noise but not step 1? No amount of hardware averaging reduce SNR step 0. It seems the issue step 0 worsens as PWM external drive voltage is increased and is highly unexpected behavior. If it were EMI effecting ADC1 sequencer 1 step 0 why would step 1 not show any sign of increased SNR?

Notice DC comparators are providing triggers for PWM0 fault monitoring tied into generator blocks digital comparators as 3 OR'd faults. Perhaps there is a Tivaware underlying issue to properly configure hardware for 3 OR'd trigger inputs into the PWM module? Perhaps a violation on the hardware level as one DC comparator threshold triggers 3 digital comparators of PWM generators?  Would code below not be one of several possible logical methods required to configure multiple PWM generator fault behaviors? Datasheet text is not suggesting any such violation possible. However it was prudent to make 3 analog comparator outputs OD tied into 3 PWMnFaults input pins OR'd in a similar way.    

MAP_ADCSequenceStepConfigure(ADC1_BASE, 1, 0, PIN_MOSTEMP_HIGH1);//AIN9
      MAP_ADCSequenceStepConfigure(ADC1_BASE, 1, 1, PIN_MOSTEMP_LOW1);//AIN16
      MAP_ADCSequenceStepConfigure(ADC1_BASE, 1, 2, PIN_MOSTEMP_HIGH1 | ADC_CTL_CMP0);
      MAP_ADCSequenceStepConfigure(ADC1_BASE, 1, 3, PIN_MOSTEMP_LOW1| ADC_CTL_CMP1 |
                                                         ADC_CTL_END | ADC_CTL_IE);

   /* Configure the extended fault group-1 trigger sources for ADC1 DCMP0/1 MOSTEMP-L/H
    * ADC0 Digital comparators as fault source (MINFLTPER[0],LATCH[1]/PWMCTLn) */
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_0, PWM_FAULT_GROUP_1,
    							PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1);
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_1, PWM_FAULT_GROUP_1,
    							PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1);
    MAP_PWMGenFaultTriggerSet(PWM0_BASE, PWM_GEN_2, PWM_FAULT_GROUP_1,
    							PWM_FAULT_DCMP0 | PWM_FAULT_DCMP1);

4 Replies

  • Hi BP101,
    The fact that you get this error on the first channel of the sequence, regardless of which channel that is, makes me think there is a residual voltage on the sample capacitor that did not equalize. One thing to try would be to increase the sample time to see if that helps. Are you converting any other channels with a different sequencer on ADC1? If so, the channel previously converted may be the one affecting the first channel converted on sequence 1.

    Best Regards,
    Bob Crosby

  • Guru 47685 points

    In reply to Bob Crosby:

    Hi Bob,

    Bob Crosby
    Are you converting any other channels with a different sequencer on ADC1?

    Only these two channels active on ADC1 and step hold value has no effect to reduce the rolling FIFO values on step 0 even if sequencer 1 is selected. Being PWM is involved it stands to reason COMP0 is the culprit since it remained on step 0 for both channels. 

    Group1 triggers into each generator all share COMP0, should they? There are 8 digital comparators, perhaps each generator expects an isolated ADC trigger as not to share COMP0/1 between all 3 generators? The datasheet block diagram of PWM generator is not giving a broad view of group 1 fault architecture. Seemingly the PWM generators fault group 1 OR gate output must be OD for sharing COMP0 between generators? Simply configuring each specific generator to share the same COMP0 or COMP1 may not be (fully) hardware compatible, even though Tivaware ASSERT allows such configurations?

  • In reply to Gl:

    BP101
    Only these two channels active on ADC1 and step hold value has no effect to reduce the rolling FIFO values on step 0 even if sequencer 1 is selected. Being PWM is involved it stands to reason COMP0 is the culprit since it remained on step 0 for both channels

    What are you using to trigger the ADC1 conversion? If triggered from one of the PWMs, the offset may just be a result of the switching noise. In that case adding a dummy conversion as the first conversion of the sequence to push the other conversions past the time of the noise may be your best solution.

    BP101
    Group1 triggers into each generator all share COMP0, should they? There are 8 digital comparators, perhaps each generator expects an isolated ADC trigger as not to share COMP0/1 between all 3 generators?

    It is perfectly acceptable to have a single ADC comparator trigger multiple PWM generator faults.

    Best Regards,
    Bob Crosby

  • Guru 47685 points

    In reply to Bob Crosby:

    Bob Crosby
    What are you using to trigger the ADC1 conversion?

    Trigger_Processor in one second intervals. 

    Bob Crosby
    It is perfectly acceptable to have a single ADC comparator trigger multiple PWM generator faults.

    Apparently not on the other side of the fault group 1 OR gate. The fault group 1 no longer phantom triggers from step 0 results after configuring 6 DC comparators, e.g. 3 for high and 3 for low fault drives. The odd part is all 6 DC comparators OR for each generator fault group 1 but electrically divide low from high temperature threshold at the sequencer steps 0/1. Somehow such a configuration creates COMP0 isolation for PWM triggers bleeding noise into the step 0 sample FIFO results. Anyway that method produces much more stable temperature readings both steps 0/1.

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