TM4C123GH6ZRB: CAN bus timing limitation between two messages

TISL

Expert 3795 points

Part Number: TM4C123GH6ZRB

Dear e2e Support,

My customer uses our TM4C123GH6ZRB in a one to one CAN architecture.

They've noticed that for a use at 500kbit/s, a 1ms delay is needed between two CAN messages of 100bits each.

Could you confirm if there is a hardware limitation from our side?

Their need is to go up to 3 messages per ms.

Regards,

besoin est d’aller jusqu’à 3 messages par ms.

over 5 years ago

0 Bob Crosby over 5 years ago

TI__Guru 72500 points

There is no such hardware limitation on the TM4C123. They may want to look at the CAN bus with a logic analyzer that decodes the CAN protocol to see if there are any retransmissions because of bus faults.

Arm-based microcontrollers

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TM4C123GH6ZRB: CAN bus timing limitation between two messages