TM4C129XKCZAD: EPIOS Bus

Hi John,

John Smith2 said:

Is EPIOS a self clocking system or do certain lines (for optimum performance of the EPIOS bus), have to go to a clock input if (for example) one was interfacing between this uController and an FPGA?

 One of the supported modes by the EPI module is the general purpose mode which can provide clock to your FPGA.

Below is the excerpt from the datasheet. Please refer to the device datasheet for details. 

11.4.4 General-Purpose Mode
The General-Purpose Mode Configuration (EPIGPCFG) register is used to configure the control,
data, and address pins, if used. Any unused EPI controller signals can be used as GPIOs or another
alternate function. The general-purpose configuration can be used for custom interfaces with FPGAs,
CPLDs, and digital data acquisition and actuator control.
General-Purpose mode is designed for three general types of use:
■ Extremely high-speed clocked interfaces to FPGAs and CPLDs. Three sizes of data and optional
address are supported. Framing and clock-enable functions permit more optimized interfaces.
■ General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely
controlled by the EPIBAUD register baud rate (when used with the WFIFO and/or the NBRFIFO)
or by the rate of accesses from software or μDMA. Examples of this type of use include:

– Reading 20 sensors at fixed time periods by configuring 20 pins to be inputs, configuring the
COUNT0 field in the EPIBAUD register to some divider, and then using non-blocking reads.
– Implementing a very wide ganged PWM/PCM with fixed frequency for driving actuators, LEDs,
etc.
■ General custom interfaces of any speed.
The configuration allows for choice of an output clock (free-running or gated), a framing signal (with
frame size), a ready input (to stretch transactions), an address (of varying sizes), and data (of varying
sizes). Additionally, provisions are made for separating data and address phases.
The interface has the following optional features:
■ Use of the EPI clock output is controlled by the CLKPIN bit in the EPIGPCFG register. Unclocked
uses include general-purpose I/O and asynchronous interfaces (optionally using RD and WR
strobes). Clocked interfaces allow for higher speeds and are much easier to connect to FPGAs
and CPLDs (which usually include input clocks).
■ EPI clock, if used, may be free running or gated depending on the CLKGATE bit in the EPIGPCFG
register. A free-running EPI clock requires another method for determining when data is live,
such as the frame pin or RD/WR strobes. A gated clock approach uses a setup-time model in
which the EPI clock controls when transactions are starting and stopping. The gated clock is
held high until a new transaction is started and goes high at the end of the cycle where
RD/WR/FRAME and address (and data if write) are emitted.

John Smith2 said:

do some of the lines of the EPIOS bus have specific functions in some modes?

Yes. As mentioned the EPI can be configured for different modes: SDRAM, Host-bus and General Purpose modes. For different modes, different EPI lines can have different functionalities. For example, in SDRAM mode the EPI0S30 line is for CKE (clock enable) but in Host-Mode the same line is used for CSn (chip select) while in General-purpose mode the EPI0S30 is used as a Frame signal. So it depends which mode you select.