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Part Number: TM4C1299NCZAD
When VDD and VDDA are connected to the same power supply, VDDC begins to be generated when VDD reaches about 2.5V when the power is turned on.
If the rise rate of VDD is very slow, even when VDDC reaches 1.2V, VDD remains at about 2.5V.
Is this situation not adversely affecting the internal power supply circuit?
Although the mysterious burning of TM4C1299NCZAD continues, it is known that there is no problem with the external circuit.
I suspect that this situation is adversely affected.
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In reply to Ralph Jacobi:
As far as I have examined, neither the data sheet nor the system design guidelines nor the silicon errata describe the possibility of chip burning due to the relationship between VDD / VDDA and VDDC.
I made three types of printed circuit boards with the same peripheral circuit using TM4C1299NCZAD, but mysterious burnout is caused by two types of printed circuit boards where VDD / VDDA is connected to the same power supply and rises slowly.However, burnout does not occur in one type of printed circuit board in which VDDA rises after VDD.
Since the difference is about the voltage of VDD / VDDA when VDDC is generated, I thought there might be a limitation of the VDDC power supply that has not been clarified.
user6220457Although the mysterious burning of TM4C1299NCZAD continues, it is known that there is no problem with the external circuit.
May it be asked:
From experience - such 'unusual' power supply performance (may) indicate the presence of, 'Voltage Transients' (especially at Turn-On) - which exceed the MCU's specifications - and are 'Known MCU Killers!'
In reply to user6220457:
I also would like to get the answers from cb1's list of key questions, so please take time to address them as well.
In addition, I would like to understand more about this burnout case when it occurs.
Lastly, can you share waveforms for the VDD/VDDA rise that is supposedly a cause of this problem?
user6220457Although the mysterious burning of TM4C1299NCZAD continues
Does not equal 'mystery' befall the (always) 'helpful:'
It proves useful if this list is amended to the one provided for you earlier along w/Vendor Ralph's probing.
Note too that a 'Slowed 3V3 Rise' - may not be 'appreciated' by other ICs/devices on your custom board - & should those have become damaged - and 'connect to your MCU' - issues (i.e. 'burning') may result...
And finally - as a, 'Sanity Check' - this vendor produces, 'Tens of Thousands of these MCUs.' You should properly 'compare/contrast' the 'MCU's, Design, Development, Production' excellence ... with that of your, 'Unnamed, slow-rise, (apparently) troublesome power supply.' 'David' - only rarely - beats 'Goliath' - and it is almost certain - this is not one of those occasions... (Odds are high on a, 'Flawed power supply and/or board irregularity' - focus there appears a, superior direction...)
In reply to cb1_mobile:
Thank you for your answers.
I am impressed that you are thinking seriously.
I'll give you a little more specific information.
・5V is generated from 24V with APXW005A0X3-SRZ (ABB Embedded Power), and 3.3V generated with EN5337QI (ALTERA) from this 5V is input to VDD / VDDA.
・The same 3.3V is used as the power supply for CPU peripheral circuits.
・The same 3.3V is connected to VBAT,VREF+.
・The 3.3V (VDD) output rate of EN5337QI is set to 0.003V/us so that the VBAT rise rate is less than 0.7V/us.
This is in accordance with ELEC # 02 of Silicon Errata “Tiva ™ C Series TM4C129x Microcontrollers Silicon Revisions 1, 2, and 3”.
The silicon revision is 3.
・3.3V (VDD) starts to be output when the 5V input reaches about 2.15V, but since the 5V rise rate is 0.00026V/us, 3.3V (VDD) rises to about 2.35V. 3.3V (VDD) catches up to 5V input.
After that, 3.3V (VDD) rises at the same rate as 5V input.
・VDDC starts to rise when VDD is 2.36V and reaches 1.2V when VDD becomes 2.39V.
・The two burned CPUs were analyzed by TI, and the result was that the device was exposed to voltage conditions outside the specified range of use. (QEM-CCR-1906-01054) "TI electrical testing verified the issue and the root cause was determined to be Electrically Induced Physical Damage (EIPD).
Electrical testing of the customer return units found several pins with Opens/Shorts fails.
This supports the external damage noted on the package.
Data indicates that the devices were subjected to a voltage condition outside of the specified usage range."
・However, all power pins (VDD, VDDA, VBAT, VREFA +) are connected to 3.3V of EN5337QI output, and all GND pins (GND, GNDA, GNDX, GNDX2, VREF-) are connected to 0V.
Also, since the peripheral circuit is driven at 3.3V, which is the same as VDD, it is unlikely that a voltage exceeding the maximum rating will be applied to the IO pin.
As a result, I have stopped moving forward.
I will explain the situation.
Board A: 7 out of 45 boards burned or malfunctioned.
Board B: 3 out of 17 boards burned or malfunctioned.
Thank you - your presentation of such exhaustive data is both welcome & much appreciated. Your inclusion of the, 'KEY Voltages at Power-Up' (via scope cap) proves especially useful - well done!
I will follow your order of presentation:
"3.3V generated with EN5337QI (ALTERA) from this 5V is input to VDD / VDDA."
You meant, "3V3 is input (not 5V) to VDD/VDDA" - did you not?
" two burned CPUs were analyzed by TI, the result was that the device was exposed to voltage conditions outside the specified range of use."
This was as I had earlier suspected.
"Electrical testing of the customer return units found several pins with Opens/Shorts fails."
This is unfortunately vague! Did not the vendor analysis 'identify' those 'damaged pins?' Especially useful would be, 'Power Pin failures' - yet such is (apparently) 'unknown!' Should, 'Non Power Pins' (i.e. ideally GPIO) have been found 'faulty' - tracing them to their, 'Peripheral Sources' - proves (highly likely) to have identified your, 'Fault Agent!'
"since the peripheral circuit is driven at 3.3V, which is the same as VDD, it is unlikely that a voltage exceeding the maximum rating will be applied to the IO pin."
May I note that 'unlikely' does not rise to, 'Never!' Usually - it is my firm's finding - that, 'Peripheral chips prove more robust' than their, 'MCU counterparts!' (from ALL Vendors - this likely due to the greater complexity (thus vulnerability) embedded w/in the 'mixed signal MCU.')
Hopefully something herein proves 'Guiding and/or otherwise useful' - such is our objective... Best of luck - and (perhaps further) analysis...
I review the QEM report, thank you for sharing the exact one as I do have the ability to look it up.
Based on the findings in the report, and the voltage ramp image posted above, I am seeing no reason to come to any sort of conclusion that VDDC is impacted by VDD/VDDA slow rise time in the way you have stated, or that you have uncovered an unknown errata item for the device. I'm honestly a bit perplexed where the idea of that possibility came from as nothing in the report would indicate to me to even look in such a direction.
I don't want to share details of the report on here to protect confidential information, but I have seen nothing that calls into question the conclusions from it that this is overvoltage situation.
I would recommend you read through cb1's commentary on how to try and debug this further at a system level - he has given many points of good advice.
The note “VDDA must be powered up before VDD” written in the TM4C1294 MCU Manual could also be found in the TM4C1299 MCU Manual.
I missed this note completely.
The reason why the rise timing of VDDC was suspected was because there was no burnout failure on the board where the rise of VDDC was sufficiently slower than the rise of VDD.
Review the peripheral circuit and look for the possibility of overvoltage.
Thank you everyone.
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