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TM4C123FH6PM: Questions about interrupt jump

Part Number: TM4C123FH6PM

Hello.

Q1> I cannot jump from Main () to ISR(ButtonKeyIntHandler) when the PA [2] through PA[5] button is pressed.

        Please explain what is wrong 

Best Regards,

Jame,Shin

ButtonKeyIntHandler ( )

{

     uint32_t ui32Ints;

     ui32Ints = GPIOIntStatus(GPIO_PORTA_BASE, true);

     if(ui32Ints == GPIO_INT_PIN_2)

     {

        ....

     }

     if(ui32Ints == GPIO_INT_PIN_3)

     {

       ....

     }

    if(ui32Ints == GPIO_INT_PIN_4)

    {

      ....

     }

    if(ui32Ints == GPIO_INT_PIN_5)

    {

      ....

     }

 

 }

 

Main( )

{

            ..

   // Set for Interrupt Configure GPIO PA[2], PA[3], PA[4]; PA[5]

  //

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

  GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5,  GPIO_STRENGTH_8MA,GPIO_PIN_TYPE_STD_WPU);

  GPIOIntTypeSet(GPIO_PORTA_BASE, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5, GPIO_FALLING_EDGE);

  GPIOIntRegister(GPIO_PORTA_BASE, ButtonKeyIntHandler);

  //

  // GPIO Commit Control PA[5:2], GPIO Lock

  //

  HWREG(GPIO_PORTA_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;

  HWREG(GPIO_PORTA_BASE + GPIO_O_CR) |= (GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5);

   ….

  GPIOIntEnable(GPIO_PORTA_BASE, GPIO_INT_PIN_2|GPIO_INT_PIN_3|GPIO_INT_PIN_4|GPIO_INT_PIN_5);

   while(1)

   {

     ..

   }

}

  • Interrupt-Free Greetings,

    Once again - young staff, "Feels (yet does not share) your Pain."

    Might you consider:

    •  You chose, "GPIOIntRegister()" - which configures the interrupt at "run-time."    The MCU manual (then) advises: "Run-time configuration of interrupt handlers requires that the interrupt handler table be placed on a 1-kB boundary in SRAM (typically this is at the beginning of SRAM). Failure to do so results in an incorrect vector address being fetched in response to an interrupt."    Young staff thus asks - "Had you noted (and complied) w/that extra demand & detailing?"
    • In addition - the MCU manual goes on to note, "Run-time configuration of interrupts adds a small latency to the interrupt response time because the stacking operation (a write to SRAM) and the interrupt handler table fetch (a read from SRAM) must be performed sequentially."    Staff thus asks, "Why would you 'Add Effort' and be penalized (via slowed response time) in that process?
    • The manual proceeds to note, "Interrupt handlers can be configured in one of two ways; statically at compile time or dynamically at run time. Static configuration of interrupt handlers is accomplished by editing the interrupt handler table in the application’s startup code.   Statically configuring the interrupt table provides the fastest interrupt response time."   Does it not appear that "statically configuring" is a vastly (eased), faster responding - thus superior choice?

    While PA2-PA5 (pins you chose for "Switch/Button Use" (default) to SPI) - we're unsure if they require "Un-Locking."   Again the MCU manual (w/in the Lock/Unlock Register Pair description - (appears) to indicate that only the "JTAG pins (4) & NMI pins (2)" -  demand such treatment.    A potential fear is that such "Unlock/Lock Attempt" may fail - and "undo" your earlier PA2-PA5 configuration.   Note too - should you have 'FIRST" (Unlocked/Locked) those pins - prior (before) you attempted to configure/reconfigure them?

    Staff suggests that one "Avoid use of any pins" (when/where possible) which demand "Special Attention."   (Inviting extra effort (i.e. trouble) is always unwise.)

    No evidence of "IntMasterEnable()" is shown - cannot hurt to include that.

    Lastly - have you (really) confirmed that your switches, "Pull their targeted pins to ground - when pressed/active?"   (as your interrupts seek a "Falling Edge.")

    It is believed that (something) herein enables your successful, "Interrupt Generation!"   (Staff (& I) see little redeeming value (yet major storm-clouds on the horizon) in the use of "IntRegister()!")    (Cast it "over-board" ... both Bob's & my sailboat - include suitable "walking planks.")

  • Hello Jame,

    In addition to

    IntMasterEnable();

    You also need:

    IntEnable(INT_GPIOA);

    Hi cb1,

    Unless customers are editing the files that handle the interrupt vector locations of the SRAM, then GPIOIntRegister will correctly place the the interrupt at the right spot. I would suspect Jame is fine on that front and really just missing the API I provided.

    That said, I do like adding ISR's manually to startup_ccs.c myself, it's much cleaner and more efficient.

    Also agree the unlock seems unnecessary.

  • Hi Ralph,

    Perhaps, "Interrupt Generating Greetings" are in order.   

    Ralph Jacobi said:
    ... GPIOIntRegister will correctly place the the interrupt at the right spot.

    Respectfully - MCU users must then, "Question the value" provided by the MCU Manual - which states:

    "Run-time configuration of interrupt handlers requires that the interrupt handler table be placed on a 1-kB boundary in SRAM (typically this is at the beginning of SRAM). Failure to do so results in an incorrect vector address being fetched in response to an interrupt.   The vector table is in a section called “vtable” and must be placed appropriately with a linker script."   Had our poster (or multiple others) prepared such a "linker script?"   

    Might there be a (slight) "Fly in the "INTEnable(INT_GPIOA)" ointment" as well?    Again from the MCU manual:

    "When using IntRegister(), the interrupt must also be enabled as before; when using the analogue in each individual driver, IntEnable() is called by the driver and does not need to be called by the application.   This appears (extremely) "Easy to MISS!"

    Staff here did note the absence of "INTEnable(INT_GPIOA)" (as you nicely noted.)    However - they (and I) believed that poster's,

    "GPIOIntEnable(GPIO_PORTA_BASE, GPIO_INT_PIN_2|GPIO_INT_PIN_3|GPIO_INT_PIN_4|GPIO_INT_PIN_5);"

    would (likely & logically) serve the 'identical purpose!'    If that's not so - an unwanted & (very) fine line exists - and may deserve (some) amplified mention w/in the (coming) latest/greatest API.   

  • Hi cb1,

    It does not.

    GPIOIntEnable enables the interrupt at a peripheral level to the GPIO peripheral is configured to fire an interrupt.

    IntEnable enables the interrupt in the NVIC in order to accept the interrupt request from the peripheral and notify the core to act upon it once it is the highest priority active interrupt.

    IntMasterEnable enables global interrupts for the MCU as a whole.

    So as it stands now, the GPIO Port A interrupt is enabled but gets stuck at the NVIC which isn't expecting an interrupt from that peripheral and thus it does not get processed by the core.

  • Greetings Ralph,

    That's a great explanation - we thank you for the added clarity.

    Do note that "Staff (somewhat) edited their original post (to which you've responded) and have "highlighted the requirement for a "Linker Script" in support of "Run-time configuration of interrupt handlers!"

    Has the MCU manual erred in so noting that Linker Script's EXTRA demand?

    All in all - as the Run-time handler demands:

    • highly detailed and ADDED effort
    • adds latency to the interrupt

    what benefits (if any) might you identify?    We cannot identify any - unless such interrupts are to be added and/or modified (by the program) on the fly!    (And just this moment has that (possible) advantage blipped our radar...)

  • Hi again, (Pest Alert increments to HIGH!)

    Staff went to the driverlib (the real legal authority for API usage) and found:

    //*****************************************************************************
    void
    GPIOIntRegister(uint32_t ui32Port, void (*pfnIntHandler)(void))
    {
    uint32_t ui32Int;

    //
    // Check the arguments.
    //
    ASSERT(_GPIOBaseValid(ui32Port));

    //
    // Get the interrupt number associated with the specified GPIO.
    //
    ui32Int = _GPIOIntNumberGet(ui32Port);

    ASSERT(ui32Int != 0);

    //
    // Register the interrupt handler.
    //
    IntRegister(ui32Int, pfnIntHandler);

    //
    // Enable the GPIO interrupt.
    //
    IntEnable(ui32Int);
    }

    Note that this agrees w/the MCU Manual - which we presented earlier.

    The (effective) burying of such function calls is sure to, "Invite Disaster" - if not immediately - then surely in time.

    Does it not appear that the (added) call to "IntEnable()" is NOT (now) Required?    (As young staff earlier asserted - and documented via MCU manual!)

    In addition - the "Peripheral Driver Library" (Interrupt Section) presents a comprehensive (GPIO rich) example - NEVER does "IntEnable()" appear!

  • Hi cb1,

    Good catch, then yes that call is accounted for. Speaking for how little I use GPIOIntRegister myself...

    Correct the added call shouldn't be required then.

    Perhaps the Master enable is the missing piece then.

    Also I wonder if the GPIO Unlock needs to be done earlier, I usually do that early on, not as one of the last steps. Something else to possible try.

    RE: benefits, I haven't had a chance to dig into that yet - still working a couple of active issues so need to sort through those to then have time for added investigation.

  • Hi Ralph,

    As I am "old school/east coast university taught" - we (really) Read the Manuals!   (as does staff - after initial reluctance.)

    You now note - as we had done earlier - that it is (almost surely) improper to "Unlock & Lock" (AFTER) those special pins have been (attempted) to be initialized/configured.   And again - young staff noted that it is doubtful that PA2-PA5 "demanded such attention!"

    Indeed - as our first (answering post) noted, the Master Interrupt Enable cannot hurt.   (Like you - I was taught, "Better to include than (hope/pray)" for its inclusion...)

    Staff & I remain concerned regarding the requirement imposed by the "Linker Script" - which the MCU manual details.   Poster has made "No mention" of that.

    Finally - should poster "retreat" from "IntRegister" (i.e. to our preferred static interrupt configuration) - then "IntEnable()" IS required!   Delightful - can you (or others) say, "Krazy Making?"

    Poster should have a "ready supply" of  Green Ink - to reward young/crack staff - for their (multiple & in-depth) findings/directives...

  • Hi cb1,

    Yeah at first it felt unnecessary but I don't remember seeing such as early. That said, the D/S wouldn't indicate it should cause an issue... but definitely something to check.

    The D/S states that setting the Commit properly allows for the corresponding GPIOAFSEL, GPIOPUR, GPIOPDR, or GPIODEN bits to be written. So I don't see anything that would undo settings there. But I'd like to see the unnecessary step removed anyways to be safe.

  • Hello,

    justice man Cb1   &   fast rabbit Ralph ,

    I'm Slow turtle, but please let me know.

    Jumped to ISR(ButtonKeyIntHandler) without setting IntMasterEnable () in the previous post.

    My lack of observation. However, NVIC needs to enable processor interrupts.

    Q1> But I don't know why ISR jumps without declaring IntMasterEnable ().

    Another interrupts don't jump(USBUART1IntHandler,..3..,..2..,..5..,USBUART7IntHandler)

    Send data from UART0, 1, 3, 2, 5, 7 module to each Rx pin.

    But only UART0 jumps ISR. UART1,3,5,7 do not jump ISR.

    Check the scope and set the break point at the same point in UARTIntClear (UART0_BASE, ui32Ints) in each ISR function.

    Q2> Why can't jump to the ISR of UART1, 3, 2, 5, 7?

           Only UART0 ISR jump(USBUARTIntHandler).

          Please explain what is wrong

    (Attach setting source code below),   Use device : TM4C123FH6PM

    ---------------------------------------------------------------------------------------------------

    (Startup.rvmdk.S) Script Declaration

    ; External declarations

    EXTERN USBUARTIntHandler

    EXTERN USBUART1IntHandler

    EXTERN USBUART3IntHandler

    EXTERN USBUART2IntHandler

    EXTERN USBUART5IntHandler

    EXTERN USBUART7IntHandler

     

    ; The vector table.

    DCD     USBUARTIntHandler           ; UART0 Rx and Tx

    DCD     USBUART1IntHandler         ; UART1 Rx and Tx

    DCD     USBUART2IntHandler         ; UART2 Rx and Tx

    DCD     USBUART3IntHandler         ; UART3 Rx and Tx

    DCD     USBUART5IntHandler         ; UART5 Rx and Tx

    DCD     USBUART7IntHandler         ; UART7 Rx and Tx

    //

    // UART0, ISR   External Function Declaration

    //

    USBUARTIntHandler(void)

    {

       uint32_t ui32Ints;

       int32_t i32Errors;

       ui32Ints = UARTIntStatus(UART0_BASE, true);

       UARTIntClear(UART0_BASE, ui32Ints);   //  Debug, break point at the same point  Check Jump OK !

       ….

    }

     

    // UART1, ISR

    USBUART1IntHandler(void)

    {

       uint32_t ui32Ints;

       int32_t i32Errors;

       ui32Ints = UARTIntStatus(UART1_BASE, true);

       UARTIntClear(UART1_BASE, ui32Ints);   //  break point at the same point  Check, No Jump !

       ….

    }

     

    // UART3, ISR

    USBUART3IntHandler(void)

    {

       uint32_t ui32Ints;

       int32_t i32Errors;

       ui32Ints = UARTIntStatus(UART3_BASE, true);

       UARTIntClear(UART3_BASE, ui32Ints);   //  break point at the same point  Check, No Jump !

       ….

    }

     

    // UART2, ISR

    USBUART2IntHandler(void)

    {

       uint32_t ui32Ints;

       int32_t i32Errors;

       ui32Ints = UARTIntStatus(UART2_BASE, true);

       UARTIntClear(UART2_BASE, ui32Ints);   //  break point at the same point  Check, No Jump !

       ….

    }

     

    // UART5, ISR

    USBUART5IntHandler(void)

    {

       uint32_t ui32Ints;

       int32_t i32Errors;

       ui32Ints = UARTIntStatus(UART5_BASE, true);

       UARTIntClear(UART5_BASE, ui32Ints);   //  break point at the same point  Check, No Jump !

       ….

    }

    // UART7, ISR

    USBUART7IntHandler(void)

    {

       uint32_t ui32Ints;

       int32_t i32Errors;

       ui32Ints = UARTIntStatus(UART7_BASE, true);

       UARTIntClear(UART7_BASE, ui32Ints);   //  break point at the same point  Check, No Jump !

       ….

    }

    Main( )

    {

    ….

    //
    // Enable the UART0,1,3,2,5,7 that we will be redirecting.
    //

    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);   // Enable the UART0
    // Wait for the UART0 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART0))
    {
    }


    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);   // Enable the UART1
    // Wait for the UART1 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART1))
    {
    }


    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART3);   // Enable the UART3
    // Wait for the UART3 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART3))
    {
    }


    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART2);   // Enable the UART2
    // Wait for the UART2 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART2))
    {
    }


    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART5);   // Enable the UART5
    // Wait for the UART5 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART5))
    {
    }


    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART7);   // Enable the UART7
    // Wait for the UART7 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART7))
    {
    }

    //

    // Enable and configure the UART0,1,3,2,5,7 RX and TX pins

    //

    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);         // PA Enable

    GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0); // U0.Rx[PA0]

    GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_1); // U0.Tx[PA1]  

     

    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);        // PC Enable

    GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4); // U1.Rx[PC4]

    GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_5); // U1.Tx[PC5]  

    GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_6); // U3.Rx[PC6]

    GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_7); // U3.Tx[PC7]  

     

    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);        // PG Enable

    GPIOPinTypeUART(GPIO_PORTG_BASE, GPIO_PIN_4); // U2.Rx[PG4]

    GPIOPinTypeUART(GPIO_PORTG_BASE, GPIO_PIN_5); // U2.Tx[PG5]

     

    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);        // PE Enable

    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_4); // U5.Rx[PE4]

    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_5); // U5.Tx[PE5]  

    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_0); // U7.Rx[PE0]

    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_1); // U7.Tx[PE1]  

     

    //

    // Set the default UART0 configuration.

    //

       UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(),

                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);

       UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);

     

    // UART1 configuration.

       UARTConfigSetExpClk(UART1_BASE, SysCtlClockGet(),

                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);

     UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);

     

    // UART3 configuration.

       UARTConfigSetExpClk(UART3_BASE, SysCtlClockGet(),

                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);

       UARTFIFOLevelSet(UART3_BASEE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);

     

    // UART2 configuration.

       UARTConfigSetExpClk(UART2_BASE, SysCtlClockGet(),

                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);

       UARTFIFOLevelSet(UART2_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);

     

    // UART5 configuration.

       UARTConfigSetExpClk(UART5_BASE, SysCtlClockGet(),

                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);

       UARTFIFOLevelSet(UART5_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);

     

    // UART7 configuration.

       UARTConfigSetExpClk(UART7_BASE, SysCtlClockGet(),

                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);

       UARTFIFOLevelSet(UART7_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);

     

     

    //

    // Configure and enable UART0 interrupts.

    //

       UARTIntClear(UART0_BASE, UARTIntStatus(UART0_BASE, false));

       UARTIntEnable(UART0_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |

                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));

     

    //  UART1 interrupts.

       ROM_UARTIntClear(UART1_BASE, UARTIntStatus(UART1_BASE        , false));

       ROM_UARTIntEnable(UART1_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |

                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));

     

    //  UART3 interrupts.

       UARTIntClear(UART3_BASE, UARTIntStatus(UART3_BASE, false));

       UARTIntEnable(UART3_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |

                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));

     

    //  UART2 interrupts.

       UARTIntClear(UART2_BASE, UARTIntStatus(UART2_BASE, false));

       UARTIntEnable(UART2_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |

                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));

     

    //  UART5 interrupts.

       UARTIntClear(UART5_BASE, UARTIntStatus(UART5_BASE, false));

       UARTIntEnable(UART5_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |

                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));

     

    //  UART7 interrupts.

       UARTIntClear(UART7_BASE, UARTIntStatus(UART7_BASE, false));

       UARTIntEnable(UART7_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |

                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));

     

    //

    // Enable interrupts now that the application is ready to start.

    //

    IntEnable(INT_UART0);        // B1 Ach

    IntEnable(INT_UART1);        // B1 Bch

    IntEnable(INT_UART3);        // B2 Ach

    IntEnable(INT_UART2);        // B2 Bch

    IntEnable(INT_UART5);        // AP Ach

    IntEnable(INT_UART7);        // AP Bch

     

    IntMasterEnable( );

       while(1)

         {

            ….

         }

    }

  • Hello Jame,

    Can you attach your startup_ccs.c file for that project? Please attach and don't text post it as the contents are very long, this way the thread doesn't get too long.

    Also in the future try and share your source code with the syntax editors for code which you can access by clicking on the symbol that looks like < / >

  • Our small tech group's (watering) eyes ... slowly recovering Greetings,

    Did the length of your "thread expanding" post "camouflage or otherwise blind us" to your, "Identification of 'How you solved' the original problem?"     (it is doubtful that (any) follow-on readers will benefit - should that "solution" be - or remain - effectively masked!)

    This thread is quickly, "Spiraling out of control" - and breaks far from your (claimed)  "Support of KISS" - which always advises, "One small Problem - and its "measured/confirmed" solution - at a time!"     This "Focus" best enables the thread to be properly classified - so that it may be effectively - "Found during a Forum-Subject Search!"

  • Hello Cb1,

    Cb1 said > "Identification of 'How you solved' the original problem?“

                       (it is doubtful that (any) follow-on readers will benefit - should that "solution" be - or remain - effectively masked!)

              A> As I mentioned in the previous poster, this is my careless observation.

                    In conclusion, the GPIO_INT_PIN_2,3,4,5 routine enters normally.

    This is explained in more detail.

    The interrupt handler is not registered in the script file. Only registered with GPIO IntRegister () function.

    And I didn't set IntMasterEnable () in the main function.

    Debugging 1> No ISR entered 1s’t breakpoint setting. (All routines, GPIO_INT_PIN_2,3,4, & 5)

    Debugging 2> Register as a script without using the IntMasterEnable () function.

    •  Question , create a thread in the E2E forum.

    Debugging 3> Confirm entering 2n’d break point setting

    •  E2E Forum Answer, IntMasterEnable () function setting is required in main function.

    Debugging 4> Using GPIOIntRegister () Function Again.

                           IntMasterEnable () setting for stable NVIC control.

    •  Asked question in the E2E forums,

    Q1> Why do ISR jump without setting the IntMasterEnable () function? (Please explain.)

    ButtonKeyIntHandler ( )

    {

          uint32_t ui32Ints;               // # <- 1st break point set

         ui32Ints = GPIOIntStatus(GPIO_PORTA_BASE, true);   // # <- 2nd break point set

         if(ui32Ints == GPIO_INT_PIN_2) // and 3 and 4, and 5

           {

           IntMasterDisable( );

           GPIOIntClear(GPIO_PORTA_BASE, GPIO_PIN_2); // and 3 and 4, and 5

           ......

           ……

           IntMasterEnable();

         }

    }

    Q2> UART0 ISR jumps but does not jump to UART1, 3, 4, 5, 7 ISR.

            Whenever data is sent to each UART port.

    Best Regards,

    Jame,Shin

  • Hello Ralph ,

    Ralph said> Can you attach your startup_ccs.c file for that project?

                  A> I'll attach it as startup_rvmdk.s file using Keil Tools.

    Ralph said> ….. you can access by clicking on the symbol that looks like < / >

                 A> Yes, I will.

    Long test times do not jump to UART1,3,2,5,7 ISR except UART0.

    Please explain what is wrong

    Best Regards,

    Jame,Shin

    This is part of revision 2.1.4.178 of the DK-TM4C123G Firmware Package.
    ;
    ;******************************************************************************
    
    ;******************************************************************************
    ;
    ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
    ;
    ;******************************************************************************
    Stack   EQU     0x00000400
    
    ;******************************************************************************
    ;
    ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
    ;
    ;******************************************************************************
    Heap    EQU     0x00000000
    
    ;******************************************************************************
    ;
    ; Allocate space for the stack.
    ;
    ;******************************************************************************
            AREA    STACK, NOINIT, READWRITE, ALIGN=3
    StackMem
            SPACE   Stack
    __initial_sp
    
    ;******************************************************************************
    ;
    ; Allocate space for the heap.
    ;
    ;******************************************************************************
            AREA    HEAP, NOINIT, READWRITE, ALIGN=3
    __heap_base
    HeapMem
            SPACE   Heap
    __heap_limit
    
    ;******************************************************************************
    ;
    ; Indicate that the code in this file preserves 8-byte alignment of the stack.
    ;
    ;******************************************************************************
            PRESERVE8
    
    ;******************************************************************************
    ;
    ; Place code into the reset code section.
    ;
    ;******************************************************************************
            AREA    RESET, CODE, READONLY
            THUMB
    
    ;******************************************************************************
    ;
    ; External declarations for the interrupt handlers used by the application.
    ;
    ;******************************************************************************
            EXTERN  SysTickIntHandler
            EXTERN  USBUARTIntHandler
    		EXTERN  USBUART1IntHandler
    		EXTERN  USBUART3IntHandler
    		EXTERN  USBUART2IntHandler
    		EXTERN  USBUART5IntHandler
    		EXTERN  USBUART7IntHandler	
            EXTERN  USB0DeviceIntHandler
    ;		EXTERN	ButtonKeyIntHandler
    
    ;******************************************************************************
    ;
    ; The vector table.
    ;
    ;******************************************************************************
            EXPORT  __Vectors
    __Vectors
            DCD     StackMem + Stack            ; Top of Stack
            DCD     Reset_Handler               ; Reset Handler
            DCD     NmiSR                       ; NMI Handler
            DCD     FaultISR                    ; Hard Fault Handler
            DCD     IntDefaultHandler           ; The MPU fault handler
            DCD     IntDefaultHandler           ; The bus fault handler
            DCD     IntDefaultHandler           ; The usage fault handler
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; SVCall handler
            DCD     IntDefaultHandler           ; Debug monitor handler
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; The PendSV handler
            DCD     SysTickIntHandler           ; The SysTick handler
            DCD     IntDefaultHandler           ; GPIO Port A
            DCD     IntDefaultHandler           ; GPIO Port B
            DCD     IntDefaultHandler           ; GPIO Port C
            DCD     IntDefaultHandler           ; GPIO Port D
            DCD     IntDefaultHandler           ; GPIO Port E
            DCD     USBUARTIntHandler           ; UART0 Rx and Tx
            DCD     USBUART1IntHandler          ; UART1 Rx and Tx
            DCD     IntDefaultHandler           ; SSI0 Rx and Tx
            DCD     IntDefaultHandler           ; I2C0 Master and Slave
            DCD     IntDefaultHandler           ; PWM Fault
            DCD     IntDefaultHandler           ; PWM Generator 0
            DCD     IntDefaultHandler           ; PWM Generator 1
            DCD     IntDefaultHandler           ; PWM Generator 2
            DCD     IntDefaultHandler           ; Quadrature Encoder 0
            DCD     IntDefaultHandler           ; ADC Sequence 0
            DCD     IntDefaultHandler           ; ADC Sequence 1
            DCD     IntDefaultHandler           ; ADC Sequence 2
            DCD     IntDefaultHandler           ; ADC Sequence 3
            DCD     IntDefaultHandler           ; Watchdog timer
            DCD     IntDefaultHandler           ; Timer 0 subtimer A
            DCD     IntDefaultHandler           ; Timer 0 subtimer B
            DCD     IntDefaultHandler           ; Timer 1 subtimer A
            DCD     IntDefaultHandler           ; Timer 1 subtimer B
            DCD     IntDefaultHandler           ; Timer 2 subtimer A
            DCD     IntDefaultHandler           ; Timer 2 subtimer B
            DCD     IntDefaultHandler           ; Analog Comparator 0
            DCD     IntDefaultHandler           ; Analog Comparator 1
            DCD     IntDefaultHandler           ; Analog Comparator 2
            DCD     IntDefaultHandler           ; System Control (PLL, OSC, BO)
            DCD     IntDefaultHandler           ; FLASH Control
            DCD     IntDefaultHandler           ; GPIO Port F
            DCD     IntDefaultHandler           ; GPIO Port G
            DCD     IntDefaultHandler           ; GPIO Port H
            DCD     USBUART2IntHandler          ; UART2 Rx and Tx
            DCD     IntDefaultHandler           ; SSI1 Rx and Tx
            DCD     IntDefaultHandler           ; Timer 3 subtimer A
            DCD     IntDefaultHandler           ; Timer 3 subtimer B
            DCD     IntDefaultHandler           ; I2C1 Master and Slave
            DCD     IntDefaultHandler           ; Quadrature Encoder 1
            DCD     IntDefaultHandler           ; CAN0
            DCD     IntDefaultHandler           ; CAN1
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; Hibernate
            DCD     USB0DeviceIntHandler        ; USB0
            DCD     IntDefaultHandler           ; PWM Generator 3
            DCD     IntDefaultHandler           ; uDMA Software Transfer
            DCD     IntDefaultHandler           ; uDMA Error
            DCD     IntDefaultHandler           ; ADC1 Sequence 0
            DCD     IntDefaultHandler           ; ADC1 Sequence 1
            DCD     IntDefaultHandler           ; ADC1 Sequence 2
            DCD     IntDefaultHandler           ; ADC1 Sequence 3
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; GPIO Port J
            DCD     IntDefaultHandler           ; GPIO Port K
            DCD     IntDefaultHandler           ; GPIO Port L
            DCD     IntDefaultHandler           ; SSI2 Rx and Tx
            DCD     IntDefaultHandler           ; SSI3 Rx and Tx
            DCD     USBUART3IntHandler          ; UART3 Rx and Tx
            DCD     IntDefaultHandler           ; UART4 Rx and Tx
            DCD     USBUART5IntHandler          ; UART5 Rx and Tx
            DCD     IntDefaultHandler           ; UART6 Rx and Tx
            DCD     USBUART7IntHandler          ; UART7 Rx and Tx
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; I2C2 Master and Slave
            DCD     IntDefaultHandler           ; I2C3 Master and Slave
            DCD     IntDefaultHandler           ; Timer 4 subtimer A
            DCD     IntDefaultHandler           ; Timer 4 subtimer B
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; Timer 5 subtimer A
            DCD     IntDefaultHandler           ; Timer 5 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 0 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 0 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 1 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 1 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 2 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 2 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 3 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 3 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 4 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 4 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 5 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 5 subtimer B
            DCD     IntDefaultHandler           ; FPU
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; I2C4 Master and Slave
            DCD     IntDefaultHandler           ; I2C5 Master and Slave
            DCD     IntDefaultHandler           ; GPIO Port M
            DCD     IntDefaultHandler           ; GPIO Port N
            DCD     IntDefaultHandler           ; Quadrature Encoder 2
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; GPIO Port P (Summary or P0)
            DCD     IntDefaultHandler           ; GPIO Port P1
            DCD     IntDefaultHandler           ; GPIO Port P2
            DCD     IntDefaultHandler           ; GPIO Port P3
            DCD     IntDefaultHandler           ; GPIO Port P4
            DCD     IntDefaultHandler           ; GPIO Port P5
            DCD     IntDefaultHandler           ; GPIO Port P6
            DCD     IntDefaultHandler           ; GPIO Port P7
            DCD     IntDefaultHandler           ; GPIO Port Q (Summary or Q0)
            DCD     IntDefaultHandler           ; GPIO Port Q1
            DCD     IntDefaultHandler           ; GPIO Port Q2
            DCD     IntDefaultHandler           ; GPIO Port Q3
            DCD     IntDefaultHandler           ; GPIO Port Q4
            DCD     IntDefaultHandler           ; GPIO Port Q5
            DCD     IntDefaultHandler           ; GPIO Port Q6
            DCD     IntDefaultHandler           ; GPIO Port Q7
            DCD     IntDefaultHandler           ; GPIO Port R
            DCD     IntDefaultHandler           ; GPIO Port S
            DCD     IntDefaultHandler           ; PWM 1 Generator 0
            DCD     IntDefaultHandler           ; PWM 1 Generator 1
            DCD     IntDefaultHandler           ; PWM 1 Generator 2
            DCD     IntDefaultHandler           ; PWM 1 Generator 3
            DCD     IntDefaultHandler           ; PWM 1 Fault
    
    ;******************************************************************************
    ;
    ; This is the code that gets called when the processor first starts execution
    ; following a reset event.
    ;
    ;******************************************************************************
            EXPORT  Reset_Handler
    Reset_Handler
            ;
            ; Enable the floating-point unit.  This must be done here to handle the
            ; case where main() uses floating-point and the function prologue saves
            ; floating-point registers (which will fault if floating-point is not
            ; enabled).  Any configuration of the floating-point unit using
            ; DriverLib APIs must be done here prior to the floating-point unit
            ; being enabled.
            ;
            ; Note that this does not use DriverLib since it might not be included
            ; in this project.
            ;
            MOVW    R0, #0xED88
            MOVT    R0, #0xE000
            LDR     R1, [R0]
            ORR     R1, #0x00F00000
            STR     R1, [R0]
    
            ;
            ; Call the C library enty point that handles startup.  This will copy
            ; the .data section initializers from flash to SRAM and zero fill the
            ; .bss section.
            ;
            IMPORT  __main
            B       __main
    
    ;******************************************************************************
    ;
    ; This is the code that gets called when the processor receives a NMI.  This
    ; simply enters an infinite loop, preserving the system state for examination
    ; by a debugger.
    ;
    ;******************************************************************************
    NmiSR
            B       NmiSR
    
    ;******************************************************************************
    ;
    ; This is the code that gets called when the processor receives a fault
    ; interrupt.  This simply enters an infinite loop, preserving the system state
    ; for examination by a debugger.
    ;
    ;******************************************************************************
    FaultISR
            B       FaultISR
    
    ;******************************************************************************
    ;
    ; This is the code that gets called when the processor receives an unexpected
    ; interrupt.  This simply enters an infinite loop, preserving the system state
    ; for examination by a debugger.
    ;
    ;******************************************************************************
    IntDefaultHandler
            B       IntDefaultHandler
    
    ;******************************************************************************
    ;
    ; Make sure the end of this section is aligned.
    ;
    ;******************************************************************************
            ALIGN
    
    ;******************************************************************************
    ;
    ; Some code in the normal code section for initializing the heap and stack.
    ;
    ;******************************************************************************
            AREA    |.text|, CODE, READONLY
    
    ;******************************************************************************
    ;
    ; The function expected of the C library startup code for defining the stack
    ; and heap memory locations.  For the C library version of the startup code,
    ; provide this function so that the C library initialization code can find out
    ; the location of the stack and heap.
    ;
    ;******************************************************************************
        IF :DEF: __MICROLIB
            EXPORT  __initial_sp
            EXPORT  __heap_base
            EXPORT  __heap_limit
        ELSE
            IMPORT  __use_two_region_memory
            EXPORT  __user_initial_stackheap
    __user_initial_stackheap
            LDR     R0, =HeapMem
            LDR     R1, =(StackMem + Stack)
            LDR     R2, =(HeapMem + Heap)
            LDR     R3, =StackMem
            BX      LR
        ENDIF
    
    ;******************************************************************************
    ;
    ; Make sure the end of this section is aligned.
    ;
    ;******************************************************************************
            ALIGN
    
    ;******************************************************************************
    ;
    ; Tell the assembler that we're done.
    ;
    ;******************************************************************************
            END
    

  • cb1_mobile said:

    Respectfully - MCU users must then, "Question the value" provided by the MCU Manual - which states:

    "Run-time configuration of interrupt handlers requires that the interrupt handler table be placed on a 1-kB boundary in SRAM (typically this is at the beginning of SRAM). Failure to do so results in an incorrect vector address being fetched in response to an interrupt.   The vector table is in a section called “vtable” and must be placed appropriately with a linker script."   Had our poster (or multiple others) prepared such a "linker script?" 

    In the TivaWare_C_Series-2.1.4.178/driverlib/interrupt.c source file the g_pfnRAMVectors vector table in RAM is marked with compiler specific attributes / pragmas to specify that the array is placed with 1024 byte alignment by the linker, i.e. on a 1-kB address boundary:

    //*****************************************************************************
    //
    // The processor vector table.
    //
    // This contains a list of the handlers for the various interrupt sources in
    // the system.  The layout of this list is defined by the hardware; assertion
    // of an interrupt causes the processor to start executing directly at the
    // address given in the corresponding location in this list.
    //
    //*****************************************************************************
    //
    // Set the size of the vector table to the largest number of interrupts of
    // any device
    //
    #undef NUM_INTERRUPTS
    #define NUM_INTERRUPTS                          155
    #if defined(ewarm)
    #pragma data_alignment=1024
    static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
    #elif defined(sourcerygxx)
    static __attribute__((section(".cs3.region-head.ram")))
    void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
    #elif defined(ccs) || defined(DOXYGEN)
    #pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
    #pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
    void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
    #else
    static __attribute__((section("vtable")))
    void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__((aligned(1024)));
    #endif

  • Thanks for that - indeed your, "Excellence in & broad knowledge of software" has long been recognized.

    Logically & from a, "Manager/Teacher's perspective" - have you not (avoided) the MCU Manual's "Cautionary Guidance" - which my staff well-quoted?    That is likely an, "Even Larger" issue - which my staff (properly) further identifies &  details...

    My university training long & loudly, "Argued Against" the (effective) BURYING of "Key Function calls, other 'help-mechanisms', and (even) such vital attributes/pragmas!"    This "help" is to be resisted as it encourages a, "Blind Dependency" upon such, "Rescue Mechanisms" - does it not?    (Do you believe - for even a second - that poster here (& others)  "recognized/knew" of the strict location  requirement?")   Is it not (almost) certain that his rescue (& that of numerous others) was, "Unplanned & Fortunate" - achieved (only) by that "Buried Location pragma's" Inclusion?

    The clear danger then - "Which functions, processes (similar)" are to receive such assistance?"   (And which - by (some) "Unknown Standard" - receive, "No such rescue?")

    The MCU Manual's rather "strong" (and repeated) warning (i.e. Place upon 1kB boundary) has thus been (effectively) rendered, "Null & Void!"    And that spot-lights an (even)   LARGER ISSUE - "Where else has the "API" produced "Clear Conflict" w/ the MCU's "Governing Authority?"   (i.e. the MCU Manual)

    Software focus alone may not prove fully sufficient - has that not been well proven?     Recognizing the "Tip of the Iceberg" - yet NOT its (below the water-line) "Bulk damage potential" - proves questionable & demands (motivation) & other re-think...

  • Hello  Cb1, Ghester, Ralph,

    Thank you for the discussion of the experts' perspectives and insights on the  interrupt jump issue.

    UART0 jumps to ISR and receives data. But UART1,3, 2, 5, 7 can't jump to ISR.

    Q1> Why do I scope-checked data inputs on each Rx pin and fail to jump to ISR?

    Q2> How do you set the correct source code should jump to ISR?

    Please explain what is wrong

    perphaps, (Other question)

    In Keil uVision Tools there is a " Preprocessor Symbols"  input in the “Options for Target” window.

    I specified it as below.

    Define : rvmdk PART_TM4C123FH6PM TARGET_IS_TM4C123_RB1 UART_BUFFERED

    Q3> What does "TARGET_IS_TM4C123_RB1 UART_BUFFERED" mean?

    Best Regards,

    Jame,Shin

    //
    
    // UART0, ISR   External Function Declaration
    
    //
    
    USBUARTIntHandler(void)
    
    {
    
       uint32_t ui32Ints;
    
       int32_t i32Errors;
    
       ui32Ints = UARTIntStatus(UART0_BASE, true);
    
       UARTIntClear(UART0_BASE, ui32Ints);   //  Debug, break point at the same point  Check Jump OK !
    
       ….
    
    }
    
     
    
    // UART1, ISR
    
    USBUART1IntHandler(void)
    
    {
    
       uint32_t ui32Ints;
    
       int32_t i32Errors;
    
       ui32Ints = UARTIntStatus(UART1_BASE, true);
    
       UARTIntClear(UART1_BASE, ui32Ints);   //  break point at the same point  Check, No Jump !
    
       ….
    
    }
    
     
    
    // UART3, ISR
    
    USBUART3IntHandler(void)
    
    {
    
       uint32_t ui32Ints;
    
       int32_t i32Errors;
    
       ui32Ints = UARTIntStatus(UART3_BASE, true);
    
       UARTIntClear(UART3_BASE, ui32Ints);   //  break point at the same point  Check, No Jump !
    
       ….
    
    }
    
     
    
    // UART2, ISR
    
    USBUART2IntHandler(void)
    
    {
    
       uint32_t ui32Ints;
    
       int32_t i32Errors;
    
       ui32Ints = UARTIntStatus(UART2_BASE, true);
    
       UARTIntClear(UART2_BASE, ui32Ints);   //  break point at the same point  Check, No Jump !
    
       ….
    
    }
    
     
    
    // UART5, ISR
    
    USBUART5IntHandler(void)
    
    {
    
       uint32_t ui32Ints;
    
       int32_t i32Errors;
    
       ui32Ints = UARTIntStatus(UART5_BASE, true);
    
       UARTIntClear(UART5_BASE, ui32Ints);   //  break point at the same point  Check, No Jump !
    
       ….
    
    }
    
    // UART7, ISR
    
    USBUART7IntHandler(void)
    
    {
    
       uint32_t ui32Ints;
    
       int32_t i32Errors;
    
       ui32Ints = UARTIntStatus(UART7_BASE, true);
    
       UARTIntClear(UART7_BASE, ui32Ints);   //  break point at the same point  Check, No Jump !
    
       ….
    
    }
    
    
    
    Main( )
    
    {
    
     ......
    
    //
    // Enable the UART0,1,3,2,5,7 that we will be redirecting.
    //
    
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);   // Enable UART0
    // Wait for the UART0 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART0))
    {
    }
    
    
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);   // Enable UART1
    // Wait for the UART1 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART1))
    {
    }
    
    
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART3);   // Enable UART3
    // Wait for the UART3 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART3))
    {
    }
    
    
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART2);   // Enable UART2
    // Wait for the UART2 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART2))
    {
    }
    
    
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART5);   // Enable UART5
    // Wait for the UART5 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART5))
    {
    }
    
    
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART7);   // Enable UART7
    // Wait for the UART7 module to be ready.
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_UART7))
    {
    }
    
    
    
    //
    
    // Enable and configure the UART0,1,3,2,5,7 RX and TX pins
    
    //
    
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);  // PA Enable
    
    GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0); // U0.Rx[PA0]
    
    GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_1); // U0.Tx[PA1]  
    
     
    
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);   // PC Enable
    
    GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4); // U1.Rx[PC4]
    
    GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_5); // U1.Tx[PC5]  
    
    GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_6); // U3.Rx[PC6]
    
    GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_7); // U3.Tx[PC7]  
    
     
    
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);  // PG Enable
    
    GPIOPinTypeUART(GPIO_PORTG_BASE, GPIO_PIN_4); // U2.Rx[PG4]
    
    GPIOPinTypeUART(GPIO_PORTG_BASE, GPIO_PIN_5); // U2.Tx[PG5]
    
     
    
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);  // PE Enable
    
    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_4); // U5.Rx[PE4]
    
    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_5); // U5.Tx[PE5]  
    
    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_0); // U7.Rx[PE0]
    
    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_1); // U7.Tx[PE1]  
    
     
    
    //
    
    // Set the default UART0 configuration.
    
    //
    
       UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(),
    
                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);
    
       UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
    
     
    
    // UART1 configuration.
    
       UARTConfigSetExpClk(UART1_BASE, SysCtlClockGet(),
    
                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);
    
     UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
    
     
    
    // UART3 configuration.
    
       UARTConfigSetExpClk(UART3_BASE, SysCtlClockGet(),
    
                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);
    
       UARTFIFOLevelSet(UART3_BASEE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
    
     
    
    // UART2 configuration.
    
       UARTConfigSetExpClk(UART2_BASE, SysCtlClockGet(),
    
                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);
    
       UARTFIFOLevelSet(UART2_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
    
     
    
    // UART5 configuration.
    
       UARTConfigSetExpClk(UART5_BASE, SysCtlClockGet(),
    
                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);
    
       UARTFIFOLevelSet(UART5_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
    
     
    
    // UART7 configuration.
    
       UARTConfigSetExpClk(UART7_BASE, SysCtlClockGet(),
    
                               DEFAULT_BIT_RATE, DEFAULT_UART_CONFIG);
    
       UARTFIFOLevelSet(UART7_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
    
     
    
     
    
    //
    
    // Configure and enable UART0 interrupts.
    
    //
    
       UARTIntClear(UART0_BASE, UARTIntStatus(UART0_BASE, false));
    
       UARTIntEnable(UART0_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |
    
                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));
    
     
    
    //  UART1 interrupts.
    
       ROM_UARTIntClear(UART1_BASE, UARTIntStatus(UART1_BASE        , false));
    
       ROM_UARTIntEnable(UART1_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |
    
                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));
    
     
    
    //  UART3 interrupts.
    
       UARTIntClear(UART3_BASE, UARTIntStatus(UART3_BASE, false));
    
       UARTIntEnable(UART3_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |
    
                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));
    
     
    
    //  UART2 interrupts.
    
       UARTIntClear(UART2_BASE, UARTIntStatus(UART2_BASE, false));
    
       UARTIntEnable(UART2_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |
    
                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));
    
     
    
    //  UART5 interrupts.
    
       UARTIntClear(UART5_BASE, UARTIntStatus(UART5_BASE, false));
    
       UARTIntEnable(UART5_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |
    
                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));
    
     
    
    //  UART7 interrupts.
    
       UARTIntClear(UART7_BASE, UARTIntStatus(UART7_BASE, false));
    
       UARTIntEnable(UART7_BASE, (UART_INT_OE | UART_INT_BE | UART_INT_PE |
    
                         UART_INT_FE | UART_INT_RT | UART_INT_TX | UART_INT_RX));
    
     
    
    //
    
    // Enable interrupts now that the application is ready to start.
    
    //
    
    IntEnable(INT_UART0);        
    
    IntEnable(INT_UART1);        
    
    IntEnable(INT_UART3);        
    
    IntEnable(INT_UART2);        
    
    IntEnable(INT_UART5);        
    
    IntEnable(INT_UART7);        
    
     
    
    IntMasterEnable( );
    
    
    
       while(1)
    
         {
    
           ......
    
         }
    
    }
    
    

    A> I'll attach it as startup_rvmdk.s file using Keil Tools.

    This is part of revision 2.1.4.178 of the DK-TM4C123G Firmware Package.
    ;
    ;******************************************************************************
    
    ;******************************************************************************
    ;
    ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
    ;
    ;******************************************************************************
    Stack   EQU     0x00000400
    
    ;******************************************************************************
    ;
    ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
    ;
    ;******************************************************************************
    Heap    EQU     0x00000000
    
    ;******************************************************************************
    ;
    ; Allocate space for the stack.
    ;
    ;******************************************************************************
            AREA    STACK, NOINIT, READWRITE, ALIGN=3
    StackMem
            SPACE   Stack
    __initial_sp
    
    ;******************************************************************************
    ;
    ; Allocate space for the heap.
    ;
    ;******************************************************************************
            AREA    HEAP, NOINIT, READWRITE, ALIGN=3
    __heap_base
    HeapMem
            SPACE   Heap
    __heap_limit
    
    ;******************************************************************************
    ;
    ; Indicate that the code in this file preserves 8-byte alignment of the stack.
    ;
    ;******************************************************************************
            PRESERVE8
    
    ;******************************************************************************
    ;
    ; Place code into the reset code section.
    ;
    ;******************************************************************************
            AREA    RESET, CODE, READONLY
            THUMB
    
    ;******************************************************************************
    ;
    ; External declarations for the interrupt handlers used by the application.
    ;
    ;******************************************************************************
            EXTERN  SysTickIntHandler
            EXTERN  USBUARTIntHandler
    		EXTERN  USBUART1IntHandler
    		EXTERN  USBUART3IntHandler
    		EXTERN  USBUART2IntHandler
    		EXTERN  USBUART5IntHandler
    		EXTERN  USBUART7IntHandler	
            EXTERN  USB0DeviceIntHandler
    ;		EXTERN	ButtonKeyIntHandler
    
    ;******************************************************************************
    ;
    ; The vector table.
    ;
    ;******************************************************************************
            EXPORT  __Vectors
    __Vectors
            DCD     StackMem + Stack            ; Top of Stack
            DCD     Reset_Handler               ; Reset Handler
            DCD     NmiSR                       ; NMI Handler
            DCD     FaultISR                    ; Hard Fault Handler
            DCD     IntDefaultHandler           ; The MPU fault handler
            DCD     IntDefaultHandler           ; The bus fault handler
            DCD     IntDefaultHandler           ; The usage fault handler
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; SVCall handler
            DCD     IntDefaultHandler           ; Debug monitor handler
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; The PendSV handler
            DCD     SysTickIntHandler           ; The SysTick handler
            DCD     IntDefaultHandler           ; GPIO Port A
            DCD     IntDefaultHandler           ; GPIO Port B
            DCD     IntDefaultHandler           ; GPIO Port C
            DCD     IntDefaultHandler           ; GPIO Port D
            DCD     IntDefaultHandler           ; GPIO Port E
            DCD     USBUARTIntHandler           ; UART0 Rx and Tx
            DCD     USBUART1IntHandler          ; UART1 Rx and Tx
            DCD     IntDefaultHandler           ; SSI0 Rx and Tx
            DCD     IntDefaultHandler           ; I2C0 Master and Slave
            DCD     IntDefaultHandler           ; PWM Fault
            DCD     IntDefaultHandler           ; PWM Generator 0
            DCD     IntDefaultHandler           ; PWM Generator 1
            DCD     IntDefaultHandler           ; PWM Generator 2
            DCD     IntDefaultHandler           ; Quadrature Encoder 0
            DCD     IntDefaultHandler           ; ADC Sequence 0
            DCD     IntDefaultHandler           ; ADC Sequence 1
            DCD     IntDefaultHandler           ; ADC Sequence 2
            DCD     IntDefaultHandler           ; ADC Sequence 3
            DCD     IntDefaultHandler           ; Watchdog timer
            DCD     IntDefaultHandler           ; Timer 0 subtimer A
            DCD     IntDefaultHandler           ; Timer 0 subtimer B
            DCD     IntDefaultHandler           ; Timer 1 subtimer A
            DCD     IntDefaultHandler           ; Timer 1 subtimer B
            DCD     IntDefaultHandler           ; Timer 2 subtimer A
            DCD     IntDefaultHandler           ; Timer 2 subtimer B
            DCD     IntDefaultHandler           ; Analog Comparator 0
            DCD     IntDefaultHandler           ; Analog Comparator 1
            DCD     IntDefaultHandler           ; Analog Comparator 2
            DCD     IntDefaultHandler           ; System Control (PLL, OSC, BO)
            DCD     IntDefaultHandler           ; FLASH Control
            DCD     IntDefaultHandler           ; GPIO Port F
            DCD     IntDefaultHandler           ; GPIO Port G
            DCD     IntDefaultHandler           ; GPIO Port H
            DCD     USBUART2IntHandler          ; UART2 Rx and Tx
            DCD     IntDefaultHandler           ; SSI1 Rx and Tx
            DCD     IntDefaultHandler           ; Timer 3 subtimer A
            DCD     IntDefaultHandler           ; Timer 3 subtimer B
            DCD     IntDefaultHandler           ; I2C1 Master and Slave
            DCD     IntDefaultHandler           ; Quadrature Encoder 1
            DCD     IntDefaultHandler           ; CAN0
            DCD     IntDefaultHandler           ; CAN1
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; Hibernate
            DCD     USB0DeviceIntHandler        ; USB0
            DCD     IntDefaultHandler           ; PWM Generator 3
            DCD     IntDefaultHandler           ; uDMA Software Transfer
            DCD     IntDefaultHandler           ; uDMA Error
            DCD     IntDefaultHandler           ; ADC1 Sequence 0
            DCD     IntDefaultHandler           ; ADC1 Sequence 1
            DCD     IntDefaultHandler           ; ADC1 Sequence 2
            DCD     IntDefaultHandler           ; ADC1 Sequence 3
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; GPIO Port J
            DCD     IntDefaultHandler           ; GPIO Port K
            DCD     IntDefaultHandler           ; GPIO Port L
            DCD     IntDefaultHandler           ; SSI2 Rx and Tx
            DCD     IntDefaultHandler           ; SSI3 Rx and Tx
            DCD     USBUART3IntHandler          ; UART3 Rx and Tx
            DCD     IntDefaultHandler           ; UART4 Rx and Tx
            DCD     USBUART5IntHandler          ; UART5 Rx and Tx
            DCD     IntDefaultHandler           ; UART6 Rx and Tx
            DCD     USBUART7IntHandler          ; UART7 Rx and Tx
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; I2C2 Master and Slave
            DCD     IntDefaultHandler           ; I2C3 Master and Slave
            DCD     IntDefaultHandler           ; Timer 4 subtimer A
            DCD     IntDefaultHandler           ; Timer 4 subtimer B
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; Timer 5 subtimer A
            DCD     IntDefaultHandler           ; Timer 5 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 0 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 0 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 1 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 1 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 2 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 2 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 3 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 3 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 4 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 4 subtimer B
            DCD     IntDefaultHandler           ; Wide Timer 5 subtimer A
            DCD     IntDefaultHandler           ; Wide Timer 5 subtimer B
            DCD     IntDefaultHandler           ; FPU
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; I2C4 Master and Slave
            DCD     IntDefaultHandler           ; I2C5 Master and Slave
            DCD     IntDefaultHandler           ; GPIO Port M
            DCD     IntDefaultHandler           ; GPIO Port N
            DCD     IntDefaultHandler           ; Quadrature Encoder 2
            DCD     0                           ; Reserved
            DCD     0                           ; Reserved
            DCD     IntDefaultHandler           ; GPIO Port P (Summary or P0)
            DCD     IntDefaultHandler           ; GPIO Port P1
            DCD     IntDefaultHandler           ; GPIO Port P2
            DCD     IntDefaultHandler           ; GPIO Port P3
            DCD     IntDefaultHandler           ; GPIO Port P4
            DCD     IntDefaultHandler           ; GPIO Port P5
            DCD     IntDefaultHandler           ; GPIO Port P6
            DCD     IntDefaultHandler           ; GPIO Port P7
            DCD     IntDefaultHandler           ; GPIO Port Q (Summary or Q0)
            DCD     IntDefaultHandler           ; GPIO Port Q1
            DCD     IntDefaultHandler           ; GPIO Port Q2
            DCD     IntDefaultHandler           ; GPIO Port Q3
            DCD     IntDefaultHandler           ; GPIO Port Q4
            DCD     IntDefaultHandler           ; GPIO Port Q5
            DCD     IntDefaultHandler           ; GPIO Port Q6
            DCD     IntDefaultHandler           ; GPIO Port Q7
            DCD     IntDefaultHandler           ; GPIO Port R
            DCD     IntDefaultHandler           ; GPIO Port S
            DCD     IntDefaultHandler           ; PWM 1 Generator 0
            DCD     IntDefaultHandler           ; PWM 1 Generator 1
            DCD     IntDefaultHandler           ; PWM 1 Generator 2
            DCD     IntDefaultHandler           ; PWM 1 Generator 3
            DCD     IntDefaultHandler           ; PWM 1 Fault
    
    ;******************************************************************************
    ;
    ; This is the code that gets called when the processor first starts execution
    ; following a reset event.
    ;
    ;******************************************************************************
            EXPORT  Reset_Handler
    Reset_Handler
            ;
            ; Enable the floating-point unit.  This must be done here to handle the
            ; case where main() uses floating-point and the function prologue saves
            ; floating-point registers (which will fault if floating-point is not
            ; enabled).  Any configuration of the floating-point unit using
            ; DriverLib APIs must be done here prior to the floating-point unit
            ; being enabled.
            ;
            ; Note that this does not use DriverLib since it might not be included
            ; in this project.
            ;
            MOVW    R0, #0xED88
            MOVT    R0, #0xE000
            LDR     R1, [R0]
            ORR     R1, #0x00F00000
            STR     R1, [R0]
    
            ;
            ; Call the C library enty point that handles startup.  This will copy
            ; the .data section initializers from flash to SRAM and zero fill the
            ; .bss section.
            ;
            IMPORT  __main
            B       __main
    
    ;******************************************************************************
    ;
    ; This is the code that gets called when the processor receives a NMI.  This
    ; simply enters an infinite loop, preserving the system state for examination
    ; by a debugger.
    ;
    ;******************************************************************************
    NmiSR
            B       NmiSR
    
    ;******************************************************************************
    ;
    ; This is the code that gets called when the processor receives a fault
    ; interrupt.  This simply enters an infinite loop, preserving the system state
    ; for examination by a debugger.
    ;
    ;******************************************************************************
    FaultISR
            B       FaultISR
    
    ;******************************************************************************
    ;
    ; This is the code that gets called when the processor receives an unexpected
    ; interrupt.  This simply enters an infinite loop, preserving the system state
    ; for examination by a debugger.
    ;
    ;******************************************************************************
    IntDefaultHandler
            B       IntDefaultHandler
    
    ;******************************************************************************
    ;
    ; Make sure the end of this section is aligned.
    ;
    ;******************************************************************************
            ALIGN
    
    ;******************************************************************************
    ;
    ; Some code in the normal code section for initializing the heap and stack.
    ;
    ;******************************************************************************
            AREA    |.text|, CODE, READONLY
    
    ;******************************************************************************
    ;
    ; The function expected of the C library startup code for defining the stack
    ; and heap memory locations.  For the C library version of the startup code,
    ; provide this function so that the C library initialization code can find out
    ; the location of the stack and heap.
    ;
    ;******************************************************************************
        IF :DEF: __MICROLIB
            EXPORT  __initial_sp
            EXPORT  __heap_base
            EXPORT  __heap_limit
        ELSE
            IMPORT  __use_two_region_memory
            EXPORT  __user_initial_stackheap
    __user_initial_stackheap
            LDR     R0, =HeapMem
            LDR     R1, =(StackMem + Stack)
            LDR     R2, =(HeapMem + Heap)
            LDR     R3, =StackMem
            BX      LR
        ENDIF
    
    ;******************************************************************************
    ;
    ; Make sure the end of this section is aligned.
    ;
    ;******************************************************************************
            ALIGN
    
    ;******************************************************************************
    ;
    ; Tell the assembler that we're done.
    ;
    ;******************************************************************************
            END