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Original question:

TM4C1290NCZAD: Master Read-access on QSSI

TM4C1290NCZAD: Latch-timing of I2C Master read

Takayuki Miyazaki
Genius 10120 points
Part Number: TM4C1290NCZAD

HI team,

I received inquiries about latch-timing of I2C Master read. Regarding SSI, customer got the comments from E2E as follows, “Normally the SSI module will use its internal clock (System Clock) to sample the the RX pin.” ( https://e2e.ti.com/support/microcontrollers/other/f/908/t/888076 )

Regarding I2C Master read, customer would like to clarify actual latch-timing of I2C Master read. Can we have advice/comments on this inquiries, please?

 

Best regards,

Miyazaki

  • 0
    TI__Guru*** 128095 points

    Hello Miyazaki-san,

    I am not sure I quite understand what exactly they want to know regarding the latch timing. Can you elaborate further specifically what timing specifications they want? A marked diagram would be the most useful here.

    I am not sure what information I'll be able to dig up since the D/S doesn't seem to indicate much there, but if I know what to look for in more detail, I can search better.

  • 0 in reply to Ralph Jacobi
    TI__Genius 10120 points

    Hello Ralph ,

    Generally, according to I2C specification, I think I2C Master latches data(SDA) by the riding edged of SCL expect start/stop condition. In this case,  if there is any refection signal (voltage step) on SCL, there is possibility that  master is not able to latch read data correctly. Usually, during changing pullup-resister, customer needs to resolve this issue. However, customer would like to know if TM4C is able to latch data correctly in this case or not. This mean, if TM4C (I2C master ) is latching data by other way, customer is considering there is not any problem even if riding edged of SCL has refection signal (voltage step) on SCL. It may be touch to comment on this, but, Can we have your advice/ comments on this inquiry , please?

     

    Best regards, Miyazaki

  • 0 in reply to Takayuki Miyazaki
    TI__Guru*** 128095 points

    Hello Miyazaki-san,

    I haven't had a chance to dig deep into this yet today, I will need to get back to you tomorrow.

  • 0 in reply to Takayuki Miyazaki
    TI__Guru*** 128095 points

    Hello Miyazaki-san,

    Regarding the issue with reflections on SCL, it is possible that such could cause issues if the VIL or VIH thresholds are crossed incorrectly as a result of these signals. For I2C, the data setup is a bit different in that it is very clock cycle dependent. Each of these requirements are outlined via the I2C Characteristics table (26-48) and so I would say they need to assess if:

    1) The reflections cross any VIH or VIL thresholds

    2) If those crossings may occur when data has been setup and is valid waiting for a good clock edge.

    Also I'll mention that the timings for I2C are covered on Figure 26-33. I2C Timing so if there are any specific timings they are concerned about, then maybe if they can highlight that and explain what they are seeing in that moment I could offer further comments.

  • 0 in reply to Ralph Jacobi
    TI__Genius 10120 points

    Hello Ralph,

    Thank you for your clarification. I shared your comments with my customer. if customer has any concerns about I2C signals, customer will open new thread.

    Best regards,

    Miyazaki