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TM4C1290NCZAD: I2CSCL/I2CSDA fall time

user5850039
Prodigy 215 points
Part Number: TM4C1290NCZAD

Hi,

We are useing TM4C1290 as I2C master.

The table26-48 in the datasheet describes that  I2CSCL/I2CSDA fall time is max 10ns.

Should we meet the spec?

I think that is much faster than I2C standard.

Best Regards,

  • 0
    TI__Guru**** 158945 points

    Hi,

      The 10nS fall time specification is what the TM4C will do as a master. It is not a requirement for other masters talking to the TM4C as a slave. The actual timing requirements for the I2C bus depend on the mode (bus speed). There is some more information in this application note: www.ti.com/.../slva695.pdf

  • 0 in reply to Charles Tsai
    Prodigy 215 points

    Hi,

    My understanding is that master TM4C can drive SCL and SDA less than 10ns fall time. Is that correct?

    If so, how about read data from slave? 10ns apply to read data?

    Beast Regards,

    Charles Tsai said:

    Hi,

      The 10nS fall time specification is what the TM4C will do as a master. It is not a requirement for other masters talking to the TM4C as a slave. The actual timing requirements for the I2C bus depend on the mode (bus speed). There is some more information in this application note: www.ti.com/.../slva695.pdf

  • 0 in reply to user5850039
    TI__Guru**** 158945 points

    HI,

     

    user5850039 said:
    My understanding is that master TM4C can drive SCL and SDA less than 10ns fall time. Is that correct?

    That is correct.

    user5850039 said:
    If so, how about read data from slave? 10ns apply to read data?

    This is not really specified. In another word, the 10ns is not what is required by the master when reading the data.