MSP432P401Y: low power modes and watchdog

Hi Carlo,

I tested in my side, the WDT can run normal in LPM3 mode.

Attach the example code I used as your reference:(WDT will reset MCU and then P1.0/LED will Blink):

#include "msp.h"


void main(void)
{
    WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD;                 // Halt watchdog timer

    // Configure GPIO
    P1->DIR |= BIT0;                        // Set P1.0 to output - SET BREAKPOINT HERE
    P1->OUT ^= BIT0;                        // Toggle P1.0

    PJ->SEL0 |= BIT0 | BIT1;                // set LFXT pin as second function

    CS->KEY = CS_KEY_VAL;                   // Unlock CS module for register access
    CS->CTL2 |= CS_CTL2_LFXT_EN;            // LFXT on

    // Loop until XT1, XT2 & DCO fault flag is cleared
    do
    {
        // Clear XT2,XT1,DCO fault flags
       CS->CLRIFG |= CS_CLRIFG_CLR_DCOR_OPNIFG |
               CS_CLRIFG_CLR_HFXTIFG |
               CS_CLRIFG_CLR_LFXTIFG |
               CS_CLRIFG_CLR_FCNTLFIFG;
       SYSCTL->NMI_CTLSTAT &= ~ SYSCTL_NMI_CTLSTAT_CS_SRC;
    } while ((SYSCTL->NMI_CTLSTAT | SYSCTL_NMI_CTLSTAT_CS_FLG)
            && (CS->IFG & CS_IFG_LFXTIFG)); // Test oscillator fault flag

    // Select ACLK as LFXTCLK
    CS->CTL1 &= ~(CS_CTL1_SELA_MASK) | CS_CTL1_SELA_0;
    // Lock CS module from unintended accesses
    CS->KEY = 0;


    // WDT 250ms, ACLK
    WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_SSEL__ACLK | WDT_A_CTL_CNTCL | WDT_A_CTL_IS_5;
    
    // Go to LPM3 mode
    // Setting the sleep deep bit
    SCB->SCR |= (SCB_SCR_SLEEPDEEP_Msk);

    // Ensures SLEEPONEXIT takes effect immediately
    __DSB();

    __sleep();
    __no_operation();                       // For debugger


}

Thanks!

Best Regards

Johnson