TMS570LC4357: DCAN Baud/Bit timing settings/calculations

Part Number: TMS570LC4357
Other Parts Discussed in Thread: LAUNCHXL2-570LC43, HALCOGEN

Hi,

I am using the Hercules LaunchPad eval board for the TMS570LC43x (LAUNCHXL2-570LC43).  I am trying to receive CAN bus traffic transmitted from another unrelated board. I have verified the can traffic is on the wire correctly, at 1 Mbit baud, with a CAN bus sniffer.   

The setting of the BTR reg depends on knowing the CAN_CLK speed, which is equivalent to the VCLK, which is selected to be PLL1. I looked at the PLL1 config reg (PLLCTL1) and it specifies 3 more components (R, NR, and NF) to determine the PLL1 frequency. Section 14.5 of the manual uses R, NR, and NF, but also introduces another variable OD.  Can you please provide an explanation of how the value of OD is determined? I'm just trying to determine a baud rate for the can bus.

Thanks!

David

  • Hello,

    The DCAN core uses VCLKA1 as clock source (CAN_CLK) for generating the CAN Bit Timing. The clock source for VCLKA1 domain is selected via the VCLKASRC register. The default source for VCLKA1 is VCLK. 

    The PLL clock is the VCO output clock divided by two prescale values (OD and R). The value of OD is an integer from 1-8 and R is an integer from 1 to 32. 

    The easy way is to use HALCoGen to configure PLL, and DCAN bit timing.

  • Yes, I think that is the way to go now. Thanks very much for your response.