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Original question:

[FAQ] TMS570LS3137: TMS570LS3137 MibSPI5 Tx and Rx with DMA

TMS570LS3137: DMA Throughput and Timing

Jaiganesh Jayaraman
Prodigy 170 points
Part Number: TMS570LS3137

Hi,

In TMS570LS31x/21x 16/32-Bit RISC Flash Microcontroller Technical Reference Manual (SPNU499C), I couldn't find the details for DMA Timing and Throughput details. I was expecting similar to Pipeline Timing and Throughput section in TMS320x2833x, 2823x Direct Memory Access (DMA) Module (SPRUFB8D).

CPU is configured for 160MHz and I understand HCLK cycle is same as CPU cycle.

I am using compatibility mode SPI  to perform frame transfer of 140 32-bit words of 1 element each. I am using CH-0 for Tx and CH-1 for Rx SPI.  

I wanted to know the cycles needed for '1' 32-bit word DMA transfer.

Thanks,

Jai

  • 0
    TI__Guru**** 186256 points

    Hello Jai,

    Unfortunately, we don't have such data written in any documents. The time it takes to transfer one element of data will depend on the number of pending channels as the DMA needs to arbitrate between channels, and will also depend on the arbitration in VBUS main SCR when multiple bus masters are accessing the same resource (e.g. the CPU and the DMA are accessing the SRAM at the same time where arbitration will take place in the main SCR (round robin scheme is used).