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Hi TI team
Could you help me to get the IEC60730 lib for MSP432 serial chips? I only find the one for MSP430.
similar as this one, www.ti.com/.../MSP430-IEC60730-SW-PACKAGE
If TI doesn't have the lib for MSP432, could you help to share us some related document to achieve the below function, thanks
Regards,
Neo
one more things. Could you share the document about how operation the general register (possible a disassembly/ instruction Set ) of MSP432. Something like the below code
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* from this software without specific prior written permission.
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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//*****************************************************************************
//
//! \addtogroup cpu_test_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
//IEC60730_pc_test.c - PC Tests for IEC60730 Class B.
//
//*****************************************************************************
#include "IEC60730_cpu_test.h"
#include "IEC60730_user_config.h"
#include "IEC60730_system_config.h"
#include <msp430.h>
static void stabilizeClocks(void);
//*****************************************************************************
//
//! Test CPU registers
//!
//! This C-callable assembly routine tests CPU core registers for stuck at bits.
//! The following registers are tested:
//! - R4
//! - SP
//! - SR
//! - R5-R15
//! The registers are tested in the order listed above
//!
//! Modified registers are \b R4, \b SP, \b SR, and \b R5-R15
//!
//! \return SIG_CPU_REG_TEST.- if test does not detects stuck at bits.
//! TEST_FAILED. - if test detects stuck at bits in CPU registers and
//! JUMP_TO_FAILSAFE is disabled in
//! "IEC60730_user_config.h".
//
//*****************************************************************************
uint8_t IEC60730_CPU_TEST_testCpuRegisters(){
// Feed WDT in case user has WDT enabled before running CPU test
#if ENABLED_WDT
uint16_t wdtConfig = WDTCTL & 0x00ff;
WDTCTL = WDTPW + WDTCNTCL + wdtConfig;
#endif // ENABLED_WDT
// First test General-Purpose Register 4 for Stuck at bits.
// If R4 passes test this register will be used to save content
// of SP, SR and R5-R15.
#if (defined(__TI_COMPILER_VERSION__) && !defined(__LARGE_CODE_MODEL__))
// Test R4
__asm(" push R4");
__asm(" mov.w #0xAAAA,R4");
__asm(" cmp.w #0xAAAA,R4");
__asm(" jne RestorePC");
__asm(" mov.w #0x5555,R4");
__asm(" cmp.w #0x5555,R4");
__asm(" jne RestorePC");
__asm(" pop R4");
// Test SP
__asm(" mov.w SP,R4");
__asm(" mov.w #0xAAAA,SP");
__asm(" cmp.w #0xAAAA,SP");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5554,SP");
__asm(" cmp.w #0x5554,SP");
__asm(" jne TestFailed");
__asm(" mov.w R4,SP");
// Test SR
// Note: SR is a 16-bit Register. and Bits 15-12 cannot be
// manipulated.
__asm(" mov SR,R4");
__asm(" mov #0xAAAA,SR");
__asm(" cmp #0xAAAA,SR");
__asm(" jne TestFailed");
__asm(" mov #0x5545,SR");
__asm(" cmp #0x5545,SR");
__asm(" jne TestFailed");
__asm(" mov R4,SR");
// Since system clock generators are modified by
// testing SR we need to wait until clocks
// are stabilized.
stabilizeClocks();
// Test R5
__asm(" mov.w R5,R4");
__asm(" mov.w #0xAAAA,R5");
__asm(" cmp.w #0xAAAA,R5");
__asm(" jne TestFailed");
__asm(" mov.w #0x5555,R5");
__asm(" cmp.w #0x5555,R5");
__asm(" jne TestFailed");
__asm(" mov.w R4,R5");
// Test R6
__asm(" mov.w R6,R4");
__asm(" mov.w #0xAAAA,R6");
__asm(" cmp.w #0xAAAA,R6");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5555,R6");
__asm(" cmp.w #0x5555,R6");
__asm(" jne TestFailed");
__asm(" mov.w R4,R6");
// Test R7
__asm(" mov.w R7,R4");
__asm(" mov.w #0xAAAA,R7");
__asm(" cmp.w #0xAAAA,R7");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5555,R7");
__asm(" cmp.w #0x5555,R7");
__asm(" jne TestFailed");
__asm(" mov.w R4,R7");
// Test R8
__asm(" mov.w R8,R4");
__asm(" mov.w #0xAAAA,R8");
__asm(" cmp.w #0xAAAA,R8");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5555,R8");
__asm(" cmp.w #0x5555,R8");
__asm(" jne TestFailed");
__asm(" mov.w R4,R8");
// Test R9
__asm(" mov.w R9,R4");
__asm(" mov.w #0xAAAA,R9");
__asm(" cmp.w #0xAAAA,R9");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5555,R9");
__asm(" cmp.w #0x5555,R9");
__asm(" jne TestFailed");
__asm(" mov.w R4,R9");
// Test R10
__asm(" mov.w R10,R4");
__asm(" mov.w #0xAAAA,R10");
__asm(" cmp.w #0xAAAA,R10");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5555,R10");
__asm(" cmp.w #0x5555,R10");
__asm(" jne TestFailed");
__asm(" mov.w R4,R10");
// Test R11
__asm(" mov.w R11,R4");
__asm(" mov.w #0xAAAA,R11");
__asm(" cmp.w #0xAAAA,R11");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5555,R11");
__asm(" cmp.w #0x5555,R11");
__asm(" jne TestFailed");
__asm(" mov.w R4,R11");
// Test R12
__asm(" mov.w R12,R4");
__asm(" mov.w #0xAAAA,R12");
__asm(" cmp.w #0xAAAA,R12");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5555,R12");
__asm(" cmp.w #0x5555,R12");
__asm(" jne TestFailed");
__asm(" mov.w R4,R12");
// Test R13
__asm(" mov.w R13,R4");
__asm(" mov.w #0xAAAA,R13");
__asm(" cmp.w #0xAAAA,R13");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5555,R13");
__asm(" cmp.w #0x5555,R13");
__asm(" jne TestFailed");
__asm(" mov.w R4,R13");
// Test R14
__asm(" mov.w R14,R4");
__asm(" mov.w #0xAAAA,R14");
__asm(" cmp.w #0xAAAA,R14");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5555,R14");
__asm(" cmp.w #0x5555,R14");
__asm(" jne TestFailed");
__asm(" mov.w R4,R14");
// Test R15
__asm(" mov.w R15,R4");
__asm(" mov.w #0xAAAA,R15");
__asm(" cmp.w #0xAAAA,R15");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mov.w #0x5555,R15");
__asm(" cmp.w #0x5555,R15");
__asm(" jne TestFailed");
__asm(" mov.w R4,R15");
// All register passed test!
__asm(" mov #0xCC,R12");
__asm(" ret");
// Stuck at bit(s) detected test failed!
__asm("RestorePC: pop R4");
__asm("TestFailed: mov #00,R12");
return TEST_FAILURE;
#else
// Test R4
__asm(" pushm.a #1,R4");
__asm(" mova #0xAAAAA,R4");
__asm(" cmp.a #0xAAAAA,R4");
__asm(" jne RestorePC");
__asm(" mova #0x55555,R4");
__asm(" cmp.a #0x55555,R4");
__asm(" jne RestorePC");
__asm(" popm.a #1,R4");
// Test SP
__asm(" mova SP,R4");
__asm(" mova #0xAAAAA,SP");
__asm(" cmp.a #0xAAAAA,SP");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55554,SP");
__asm(" cmp.a #0x55554,SP");
__asm(" jne TestFailed");
__asm(" mova R4,SP");
// Test SR
// Note: SR is a 16-bit Register. and Bits 15-12 cannot be
// manipulated.
__asm(" mov SR,R4");
__asm(" mov #0xAAAA,SR");
__asm(" cmp #0x0AAA,SR");
__asm(" jne TestFailed");
__asm(" mov #0x5545,SR");
__asm(" cmp #0x0545,SR");
__asm(" jne TestFailed");
__asm(" mov R4,SR");
// Since system clock generators are modified by
// testing SR we need to wait until clocks
// are stable.
stabilizeClocks();
// Test R5
__asm(" mova R5,R4");
__asm(" mova #0xAAAAA,R5");
__asm(" cmp.a #0xAAAAA,R5");
__asm(" jne TestFailed");
__asm(" mova #0x55555,R5");
__asm(" cmp.a #0x55555,R5");
__asm(" jne TestFailed");
__asm(" mova R4,R5");
// Test R6
__asm(" mova R6,R4");
__asm(" mova #0xAAAAA,R6");
__asm(" cmp.a #0xAAAAA,R6");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55555,R6");
__asm(" cmp.a #0x55555,R6");
__asm(" jne TestFailed");
__asm(" mova R4,R6");
// Test R7
__asm(" mova R7,R4");
__asm(" mova #0xAAAAA,R7");
__asm(" cmp.a #0xAAAAA,R7");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55555,R7");
__asm(" cmp.a #0x55555,R7");
__asm(" jne TestFailed");
__asm(" mova R4,R7");
// Test R8
__asm(" mova R8,R4");
__asm(" mova #0xAAAAA,R8");
__asm(" cmp.a #0xAAAAA,R8");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55555,R8");
__asm(" cmp.a #0x55555,R8");
__asm(" jne TestFailed");
__asm(" mova R4,R8");
// Test R9
__asm(" mova R9,R4");
__asm(" mova #0xAAAAA,R9");
__asm(" cmp.a #0xAAAAA,R9");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55555,R9");
__asm(" cmp.a #0x55555,R9");
__asm(" jne TestFailed");
__asm(" mova R4,R9");
// Test R10
__asm(" mova R10,R4");
__asm(" mova #0xAAAAA,R10");
__asm(" cmp.a #0xAAAAA,R10");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55555,R10");
__asm(" cmp.a #0x55555,R10");
__asm(" jne TestFailed");
__asm(" mova R4,R10");
// Test R11
__asm(" mova R11,R4");
__asm(" mova #0xAAAAA,R11");
__asm(" cmp.a #0xAAAAA,R11");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55555,R11");
__asm(" cmp.a #0x55555,R11");
__asm(" jne TestFailed");
__asm(" mova R4,R11");
// Test R12
__asm(" mova R12,R4");
__asm(" mova #0xAAAAA,R12");
__asm(" cmp.a #0xAAAAA,R12");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55555,R12");
__asm(" cmp.a #0x55555,R12");
__asm(" jne TestFailed");
__asm(" mova R4,R12");
// Test R13
__asm(" mova R13,R4");
__asm(" mova #0xAAAAA,R13");
__asm(" cmp.a #0xAAAAA,R13");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55555,R13");
__asm(" cmp.a #0x55555,R13");
__asm(" jne TestFailed");
__asm(" mova R4,R13");
// Test R14
__asm(" mova R14,R4");
__asm(" mova #0xAAAAA,R14");
__asm(" cmp.a #0xAAAAA,R14");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55555,R14");
__asm(" cmp.a #0x55555,R14");
__asm(" jne TestFailed");
__asm(" mova R4,R14");
// Test R15
__asm(" mova R15,R4");
__asm(" mova #0xAAAAA,R15");
__asm(" cmp.a #0xAAAAA,R15");
__asm(" jne TestFailed");
// Stack pointer is always aligned to even addresses.
__asm(" mova #0x55555,R15");
__asm(" cmp.a #0x55555,R15");
__asm(" jne TestFailed");
__asm(" mova R4,R15");
// All register passed test!
__asm(" mova #0x0001,R12");
__asm(" reta");
// Stuck at bit(s) detected test failed!
__asm("RestorePC: popm.a R4");
__asm("TestFailed: mova #0000,R12");
return TEST_FAILURE;
#endif
}
static void stabilizeClocks(void){
#if defined(__MSP430_HAS_CS__)
// To support MSP430FR2xx families FR57xx and FR2xx devices have different
// CS module functioanlity
#if defined(__MSP430FR2633) || defined(__MSP430FR2632) || defined(__MSP430FR2533) || defined(MSP430FR2532)
do
{
// Clear XT1 and DCO fault flag
CSCTL7 &= ~(XT1OFFG | DCOFFG);
// Clear OScillator fault
SFRIFG1 &= ~OFIFG;
}while (SFRIFG1&OFIFG);
#else
CSCTL0 = CSKEY;
do
{
#if (defined(XT1OFFG) && defined(XT2OFFG))
// Clear XT1 and XT2 fault flag
CSCTL5 &= ~(XT1OFFG + XT2OFFG);
#elif (defined(LFXTOFFG) && defined(HFXTOFFG))
// Clear LFXT and HFXT fault flag
CSCTL5 &= ~(LFXTOFFG + HFXTOFFG);
#endif
// Clear OScillator fault
SFRIFG1 &= ~OFIFG;
}while (SFRIFG1&OFIFG);
#endif
#elif defined(__MSP430_HAS_UCS__)
do
{
// Clear XT1 and XT2 fault flag
UCSCTL7 &= ~(XT1LFOFFG + XT2OFFG);
// Clear OScillator fault
SFRIFG1 &= ~OFIFG;
}while (SFRIFG1&OFIFG);
#elif defined(__MSP430_HAS_BC2__)
do
{
// Clear OScillator fault
IFG1 &= ~OFIFG;
}while (IFG1 & OFIFG);
#endif
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
Hello Luo,
Apologize for missing this thread. Unfortunately, I can't find anything on IEC60730 for the MSP432E401y. Also, I found this thread stating that the TM4C (sister product to MSP432E4) does not support IEC-60703, and that you can find products that do support it here: https://www.ti.com/technologies/functional-safety/overview.html
Hope this helps.
JD