TM4C123GH6PM: UART Interrupts echoing incomplete data

KMN

Part Number: TM4C123GH6PM

I've implemented the UART Interrupts on my TM4C using TivaWare functions.

The program is simple:
- an interrupt is triggered when data is received on the UART
- Each character received is echoed back between curly brackets

So if I were to send 'a' from my computer, I would get back '{a}'. Example:

The problem is when I test sending longer messages at once: the first few charaters are echoed back, then at one point there are missing characters:

EXAMPLES

Note that the messages in these example were written in full in the text field below and sent at once by pressing Enter. I'm doing this to simulate programmatically sending data over serial, which should happen as fast.

In this example, I sent the sentence 'This is a longer sentence sent for testing' :

In this example, I sent '123456789-123456789-123456789-123456789-123456789-123456789-'

Details:

- Hardware: Using a Tiva TM4C launchpad

- Using UART 0, on pins PA0 and PA1

- Baud rate : 115200, no parity, 1 stop bit, 8 bit words

The Code:

#include <stdint.h>
#include <stdbool.h> 

#include "inc/hw_memmap.h"
#include "inc/hw_types.h" 
#include "driverlib/gpio.h" 
#include "driverlib/pin_map.h" 
#include "driverlib/sysctl.h" 
#include "driverlib/uart.h"


#include "inc/hw_ints.h"
#include "driverlib/interrupt.h"


void setup(void);

int main(void) {

    //
    //  Setup
    //
    setup();

    while(1) {
       
    }
}

//****************************************************************************
//
//	UART CODE
//

void UART0_IntHandler(void) {
    //
    //  UART Interrupt Status
    //
    uint32_t ui32Status;

    //
    //  Get interrupt status
    //
    ui32Status = UARTIntStatus(UART0_BASE, true); 

    //
    // Clear interrupt flag
    //
    UARTIntClear(UART0_BASE, ui32Status); 

    //
    //  loop while there are chars
    //
    while(UARTCharsAvail(UART0_BASE))  {
        
        //
        //  Echo Character
        //
        UARTCharPutNonBlocking(UART0_BASE, '{');
        UARTCharPutNonBlocking(UART0_BASE, UARTCharGetNonBlocking(UART0_BASE));
        UARTCharPutNonBlocking(UART0_BASE, '}');
        
    }
}


//****************************************************************************
//
// SYSTEM SETUP CODE
//

//
//  UART Setup function 
//
void UARTSetup(void) {

    //****************************************
    //
    // UART0 SETUP
    //

    //
    //  Enable the clock on UART 0 and GPIO A
    //	(UART 0 is on pins PA0 and PA1)
    //	
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);

    //
    // Wait for the UART0 module to be ready.
    //
    while(!SysCtlPeripheralReady(SYSCTL_PERIPH_UART0))
    {
    }

    //
    //  Configure pins PA0 and PA1 for UART
    //
    GPIOPinConfigure(GPIO_PA0_U0RX);
    GPIOPinConfigure(GPIO_PA1_U0TX);
    GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0|GPIO_PIN_1);

    //
    //  Configure UART Settings: 
    //  UART: 0
    //  Baud rate: 115200
    //  Word length: 8
    //  Stop bits: 1
    //  Parity: None
    //
    UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(),	115200, UART_CONFIG_WLEN_8|UART_CONFIG_STOP_ONE|UART_CONFIG_PAR_NONE);
		
    //****************************************
    //
    // UART0 INTERRUPT CODE
    //

    //
    //  Enable UART0 Interrupts
    //
    IntEnable(INT_UART0);

    //
    //  Select UART0 Interrupts
    //
    UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
}


//
//	System setup
//
void setup(void) {
	
    //
    //  UART Setup function
    //
	UARTSetup();
	
    //
    //  Enable Processor Interrupts
    //
    IntMasterEnable();
}

over 6 years ago

0 Charles Tsai over 6 years ago

TI__Guru**** 159385 points

Hi,

Perhaps the write to the FIFO wasn't successful due to FIFO already full. Are you getting any FIFO full flag? Please check the returned value after you call UARTCharPutNonBlocking(). If it returns false, then the write wasn't successful and you will need to retry again.

0 KMN over 6 years ago in reply to Charles Tsai

Prodigy 60 points

Charles, First off, thanks for answering.

I've followed your suggestions and edited the part where I send to look like this :

while(UARTCharsAvail(UART0_BASE))  {

  //
  //  Echo Character
  //
  while(!UARTCharPutNonBlocking(UART0_BASE, '{')) {
    falseCount1++;
  }

  while(!UARTCharPutNonBlocking(UART0_BASE, UARTCharGetNonBlocking(UART0_BASE))) {
    falseCount2++;
  }

  while(!UARTCharPutNonBlocking(UART0_BASE, '}')) {
    falseCount3++;
  }
}

The problem here seems to be worse here :

Adding a while loop to check on the incoming character fixes this new issue, but the output is the same as the initial problem :

    //
    //  loop while there are chars
    //
    while(UARTCharsAvail(UART0_BASE))  {
			
        //
        //  Echo Character
        //
			while(!UARTCharPutNonBlocking(UART0_BASE, '{')) {
				falseCount1++;
			}

			
			while(!UART0_ReadSuccessful) {
				newCharacterIn = UARTCharGetNonBlocking(UART0_BASE);
				UART0_ReadSuccessful = (newCharacterIn == -1 ? false : true);
			}
			
			while(!UARTCharPutNonBlocking(UART0_BASE, newCharacterIn)) {
				falseCount2++;
			}
		
			while(!UARTCharPutNonBlocking(UART0_BASE, '}')) {
				falseCount3++;
			}
    }

Any Hints ?

0 Robert Adsett72 over 6 years ago in reply to KMN

Guru 10570 points

You need to decouple the read and write. Writing to the output FIFO within the receive interrupt is going to fail for any bursts above 6 characters or so. Instead receive into a buffer and transmit that separately.

Robert

0 KISHAN%20PATEL over 6 years ago

Intellectual 340 points

Hi KMN
I can understand your problem here u write something in terminal window like u write "1" this is receive like this"{1}" but u have receive after typing two or more character ......

Solution is "FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8"......here u can generate interrupt after 1/8,1/4...FIFO Is full...

0 KISHAN%20PATEL over 6 years ago in reply to KISHAN%20PATEL

Intellectual 340 points

Hi KMN this program help for u...

//********Alternate Function Selection ***********//
#define AFSELA (*((unsigned volatile long*)0x40058420)) // Alternate Function Select
#define AFSELB (*((unsigned volatile long*)0x40059420))
#define AFSELC (*((unsigned volatile long*)0x4005A420))
#define AFSELD (*((unsigned volatile long*)0x4005B420))
#define AFSELE (*((unsigned volatile long*)0x4005C420))
#define AFSELF (*((unsigned volatile long*)0x4005D420))
#define AFSELG (*((unsigned volatile long*)0x4005E420))
#define AFSELH (*((unsigned volatile long*)0x4005F420))
#define AFSELJ (*((unsigned volatile long*)0x40060420))
#define AFSELK (*((unsigned volatile long*)0x40061420))
#define AFSELL (*((unsigned volatile long*)0x40062420))
#define AFSELM (*((unsigned volatile long*)0x40063420))
#define AFSELN (*((unsigned volatile long*)0x40064420))
#define AFSELP (*((unsigned volatile long*)0x40065420))
#define AFSELQ (*((unsigned volatile long*)0x40066420))

//*******DIgital enable***********//
#define DENA (*((unsigned volatile long*)0x4005851C)) // Digital Enable port A
#define DENB (*((unsigned volatile long*)0x4005951C))
#define DENC (*((unsigned volatile long*)0x4005A51C))
#define DEND (*((unsigned volatile long*)0x4005B51C))
#define DENE (*((unsigned volatile long*)0x4005C51C))
#define DENF (*((unsigned volatile long*)0x4005D51C))
#define DENG (*((unsigned volatile long*)0x4005E51C))
#define DENH (*((unsigned volatile long*)0x4005F51C))
#define DENJ (*((unsigned volatile long*)0x4006051C))
#define DENK (*((unsigned volatile long*)0x4006151C))
#define DENL (*((unsigned volatile long*)0x4006251C))
#define DENM (*((unsigned volatile long*)0x4006351C))
#define DENN (*((unsigned volatile long*)0x4006451C))
#define DENP (*((unsigned volatile long*)0x4006551C))
#define DENQ (*((unsigned volatile long*)0x4006651C))

//******* Analog Mode Select (AMSEL), offset 0x528****//
#define AMSELA (*((unsigned volatile long*)0x40058528))
#define AMSELB (*((unsigned volatile long*)0x40059528))
#define AMSELC (*((unsigned volatile long*)0x4005A528))
#define AMSELD (*((unsigned volatile long*)0x4005B528))
#define AMSELE (*((unsigned volatile long*)0x4005C528))
#define AMSELF (*((unsigned volatile long*)0x4005D528))
#define AMSELG (*((unsigned volatile long*)0x4005E528))
#define AMSELH (*((unsigned volatile long*)0x4005F528))
#define AMSELJ (*((unsigned volatile long*)0x40060528))
#define AMSELK (*((unsigned volatile long*)0x40061528))
#define AMSELL (*((unsigned volatile long*)0x40062528))
#define AMSELM (*((unsigned volatile long*)0x40063528))
#define AMSELN (*((unsigned volatile long*)0x40064528))
#define AMSELP (*((unsigned volatile long*)0x40065528))
#define AMSELQ (*((unsigned volatile long*)0x40066528))

//******** INPUT OUTPUT (DIR)*******//
#define DIRA (*((unsigned volatile long*)0x40058400)) // Direction PG-760
#define DIRB (*((unsigned volatile long*)0x40059400))
#define DIRC (*((unsigned volatile long*)0x4005A400))
#define DIRD (*((unsigned volatile long*)0x4005B400))
#define DIRE (*((unsigned volatile long*)0x4005C400))
#define DIRF (*((unsigned volatile long*)0x4005D400))
#define DIRG (*((unsigned volatile long*)0x4005E400))
#define DIRH (*((unsigned volatile long*)0x4005F400))
#define DIRJ (*((unsigned volatile long*)0x40060400))
#define DIRK (*((unsigned volatile long*)0x40061400))
#define DIRL (*((unsigned volatile long*)0x40062400))
#define DIRM (*((unsigned volatile long*)0x40063400))
#define DIRN (*((unsigned volatile long*)0x40064400))
#define DIRP (*((unsigned volatile long*)0x40065400))
#define DIRQ (*((unsigned volatile long*)0x40066400))

//********** Data (DATA)***********[9-2]//
#define DATAA (*((unsigned volatile long*)0x400583FC)) // Data PG-759
#define DATAB (*((unsigned volatile long*)0x400593FC))
#define DATAC (*((unsigned volatile long*)0x4005A3FC))
#define DATAD (*((unsigned volatile long*)0x4005B3FC))
#define DATAE (*((unsigned volatile long*)0x4005C3FC))
#define DATAF (*((unsigned volatile long*)0x4005D3FC))
#define DATAG (*((unsigned volatile long*)0x4005E3FC))
#define DATAH (*((unsigned volatile long*)0x4005F3FC))
#define DATAJ (*((unsigned volatile long*)0x400603FC))
#define DATAK (*((unsigned volatile long*)0x400613FC))
#define DATAL (*((unsigned volatile long*)0x400623FC))
#define DATAM (*((unsigned volatile long*)0x400633FC))
#define DATAN (*((unsigned volatile long*)0x400643FC))
#define DATAP (*((unsigned volatile long*)0x400653FC))
#define DATAQ (*((unsigned volatile long*)0x400663FC))

//////******PORT CONTROL*****//////////
#define PCTLA (*((unsigned volatile long*)0x4005852C)) // PortA Control
#define PCTLB (*((unsigned volatile long*)0x4005952C))
#define PCTLC (*((unsigned volatile long*)0x4005A52C))
#define PCTLD (*((unsigned volatile long*)0x4005B52C))
#define PCTLE (*((unsigned volatile long*)0x4005C52C))
#define PCTLF (*((unsigned volatile long*)0x4005D52C))
#define PCTLG (*((unsigned volatile long*)0x4005E52C))
#define PCTLH (*((unsigned volatile long*)0x4005F52C))
#define PCTLJ (*((unsigned volatile long*)0x4006052C))
#define PCTLK (*((unsigned volatile long*)0x4006152C))
#define PCTLL (*((unsigned volatile long*)0x4006252C))
#define PCTLM (*((unsigned volatile long*)0x4006352C))
#define PCTLN (*((unsigned volatile long*)0x4006452C))
#define PCTLP (*((unsigned volatile long*)0x4006552C))
#define PCTLQ (*((unsigned volatile long*)0x4006652C))

//////*****LOCK CONTROL***FOR UNLOCK ENTER 0x4C4F434B* PG-777//
#define LOCKA (*((unsigned volatile long*)0x40058520))//pg777 LOCK
#define LOCKB (*((unsigned volatile long*)0x40059520))
#define LOCKC (*((unsigned volatile long*)0x4005A520))
#define LOCKD (*((unsigned volatile long*)0x4005B520))
#define LOCKE (*((unsigned volatile long*)0x4005C520))
#define LOCKF (*((unsigned volatile long*)0x4005D520))
#define LOCKG (*((unsigned volatile long*)0x4005E520))
#define LOCKH (*((unsigned volatile long*)0x4005F520))
#define LOCKJ (*((unsigned volatile long*)0x40060520))
#define LOCKK (*((unsigned volatile long*)0x40061520))
#define LOCKL (*((unsigned volatile long*)0x40062520))
#define LOCKM (*((unsigned volatile long*)0x40063520))
#define LOCKN (*((unsigned volatile long*)0x40064520))
#define LOCKP (*((unsigned volatile long*)0x40065520))
#define LOCKQ (*((unsigned volatile long*)0x40066520))

//******CLOCK GIVING FOR INDIVIDUAL PORT******//
//[0---A,1--B,...14-Q]//

#define RCGCGPIO (*((unsigned volatile long*)0x400FE608)) //CLOCK GIVING PG-382
///////////////////////////////////////////////

#define PURJ (*((unsigned volatile long*)0x40060510))//PULL UP resiator

//////////******UART0************///////////////////
#define RCGCUART (*((unsigned volatile long*)0x400FE618))//UART GETTING CLK PG-385 FOR UARt0 0x01
#define UARTCTL (*((unsigned volatile long*)0x4000C030))//UART CONTROLL PG-1182
#define UARTIBRD (*((unsigned volatile long*)0x4000C024))//Integer Baud-Rate PG-1178
#define UARTFBRD (*((unsigned volatile long*)0x4000C028))//Fractional Baud-Rate Pg-1179
#define UARTLCRH (*((unsigned volatile long*)0x4000C02C))//UART Line Control pg-1180
#define UARTCC (*((unsigned volatile long*)0x4000CFC8))//UART Clock Configuration PG-1207
#define UARTDR (*((unsigned volatile long*)0x4000C000))//UART DATA PG-1169
#define UARTFR (*((unsigned volatile long*)0x4000C018))//UART INTRRUPT PG-1174
#define UARTIM (*((unsigned volatile long*)0x4000C038))//UART INT MASK
#define UARTICR (*((unsigned volatile long*)0x4000C044))//INT CLEAR PG-1200
#define UARTRIS (*((unsigned volatile long*)0x4000C03C))
#define UARTIFLS (*((unsigned volatile long*)0x4000C034))//UART Interrupt FIFO Level Select
/////////////*******ADC********/////////
#define RCGCADC (*((unsigned volatile long*)0x400FE638)) // ADC CLOCK giving SELECTION
//*****************************************************************************
//
// ADC registers (ADC0)
//
//*****************************************************************************
#define ADC0ACTSS (*((unsigned volatile long*)0x40038000))
#define ADC0RIS (*((unsigned volatile long*)0x40038004))
#define ADC0IM (*((unsigned volatile long*)0x40038008))
#define ADC0ISC (*((unsigned volatile long*)0x4003800C))
#define ADC0OSTAT (*((unsigned volatile long*)0x40038010))
#define ADC0EMUX (*((unsigned volatile long*)0x40038014))
#define ADC0USTAT (*((unsigned volatile long*)0x40038018))
#define ADC0TSSEL (*((unsigned volatile long*)0x4003801C))
#define ADC0SSPRI (*((unsigned volatile long*)0x40038020))
#define ADC0SPC (*((unsigned volatile long*)0x40038024))
#define ADC0PSSI (*((unsigned volatile long*)0x40038028))
#define ADC0SAC (*((unsigned volatile long*)0x40038030))
#define ADC0DCISC (*((unsigned volatile long*)0x40038034))
#define ADC0CTL (*((unsigned volatile long*)0x40038038))
#define ADC0SSMUX0 (*((unsigned volatile long*)0x40038040))
#define ADC0SSCTL0 (*((unsigned volatile long*)0x40038044))
#define ADC0SSFIFO0 (*((unsigned volatile long*)0x40038048))
#define ADC0SSFSTAT0 (*((unsigned volatile long*)0x4003804C))
#define ADC0SSOP0 (*((unsigned volatile long*)0x40038050))
#define ADC0SSDC0 (*((unsigned volatile long*)0x40038054))
#define ADC0SSEMUX0 (*((unsigned volatile long*)0x40038058))
#define ADC0SSTSH0 (*((unsigned volatile long*)0x4003805C))
#define ADC0SSMUX1 (*((unsigned volatile long*)0x40038060))
#define ADC0SSCTL1 (*((unsigned volatile long*)0x40038064))
#define ADC0SSFIFO1 (*((unsigned volatile long*)0x40038068))
#define ADC0SSFSTAT1 (*((unsigned volatile long*)0x4003806C))
#define ADC0SSOP1 (*((unsigned volatile long*)0x40038070))
#define ADC0SSDC1 (*((unsigned volatile long*)0x40038074))
#define ADC0SSEMUX1 (*((unsigned volatile long*)0x40038078))
#define ADC0SSTSH1 (*((unsigned volatile long*)0x4003807C))
#define ADC0SSMUX2 (*((unsigned volatile long*)0x40038080))
#define ADC0SSCTL2 (*((unsigned volatile long*)0x40038084))
#define ADC0SSFIFO2 (*((unsigned volatile long*)0x40038088))
#define ADC0SSFSTAT2 (*((unsigned volatile long*)0x4003808C))
#define ADC0SSOP2 (*((unsigned volatile long*)0x40038090))
#define ADC0SSDC2 (*((unsigned volatile long*)0x40038094))
#define ADC0SSEMUX2 (*((unsigned volatile long*)0x40038098))
#define ADC0SSTSH2 (*((unsigned volatile long*)0x4003809C))
#define ADC0SSMUX3 (*((unsigned volatile long*)0x400380A0))
#define ADC0SSCTL3 (*((unsigned volatile long*)0x400380A4))
#define ADC0SSFIFO3 (*((unsigned volatile long*)0x400380A8))
#define ADC0SSFSTAT3 (*((unsigned volatile long*)0x400380AC))
#define ADC0SSOP3 (*((unsigned volatile long*)0x400380B0))
#define ADC0SSDC3 (*((unsigned volatile long*)0x400380B4))
#define ADC0SSEMUX3 (*((unsigned volatile long*)0x400380B8))
#define ADC0SSTSH3 (*((unsigned volatile long*)0x400380BC))
#define ADC0DCRIC (*((unsigned volatile long*)0x40038D00))
#define ADC0DCCTL0 (*((unsigned volatile long*)0x40038E00))
#define ADC0DCCTL1 (*((unsigned volatile long*)0x40038E04))
#define ADC0DCCTL2 (*((unsigned volatile long*)0x40038E08))
#define ADC0DCCTL3 (*((unsigned volatile long*)0x40038E0C))
#define ADC0DCCTL4 (*((unsigned volatile long*)0x40038E10))
#define ADC0DCCTL5 (*((unsigned volatile long*)0x40038E14))
#define ADC0DCCTL6 (*((unsigned volatile long*)0x40038E18))
#define ADC0DCCTL7 (*((unsigned volatile long*)0x40038E1C))
#define ADC0DCCMP0 (*((unsigned volatile long*)0x40038E40))
#define ADC0DCCMP1 (*((unsigned volatile long*)0x40038E44))
#define ADC0DCCMP2 (*((unsigned volatile long*)0x40038E48))
#define ADC0DCCMP3 (*((unsigned volatile long*)0x40038E4C))
#define ADC0DCCMP4 (*((unsigned volatile long*)0x40038E50))
#define ADC0DCCMP5 (*((unsigned volatile long*)0x40038E54))
#define ADC0DCCMP6 (*((unsigned volatile long*)0x40038E58))
#define ADC0DCCMP7 (*((unsigned volatile long*)0x40038E5C))
#define ADC0PP (*((unsigned volatile long*)0x40038FC0))
#define ADC0PC (*((unsigned volatile long*)0x40038FC4))
#define ADC0CC (*((unsigned volatile long*)0x40038FC8))

//*****************************************************************************
//
// ADC registers (ADC1)
//
//*****************************************************************************
#define ADC1ACTSS (*((unsigned volatile long*)0x40039000))
#define ADC1RIS (*((unsigned volatile long*)0x40039004))
#define ADC1IM (*((unsigned volatile long*)0x40039008))
#define ADC1ISC (*((unsigned volatile long*)0x4003900C))
#define ADC1OSTAT (*((unsigned volatile long*)0x40039010))
#define ADC1EMUX (*((unsigned volatile long*)0x40039014))
#define ADC1USTAT (*((unsigned volatile long*)0x40039018))
#define ADC1TSSEL (*((unsigned volatile long*)0x4003901C))
#define ADC1SSPRI (*((unsigned volatile long*)0x40039020))
#define ADC1SPC (*((unsigned volatile long*)0x40039024))
#define ADC1PSSI (*((unsigned volatile long*)0x40039028))
#define ADC1SAC (*((unsigned volatile long*)0x40039030))
#define ADC1DCISC (*((unsigned volatile long*)0x40039034))
#define ADC1CTL (*((unsigned volatile long*)0x40039038))
#define ADC1SSMUX0 (*((unsigned volatile long*)0x40039040))
#define ADC1SSCTL0 (*((unsigned volatile long*)0x40039044))
#define ADC1SSFIFO0 (*((unsigned volatile long*)0x40039048))
#define ADC1SSFSTAT0 (*((unsigned volatile long*)0x4003904C))
#define ADC1SSOP0 (*((unsigned volatile long*)0x40039050))
#define ADC1SSDC0 (*((unsigned volatile long*)0x40039054))
#define ADC1SSEMUX0 (*((unsigned volatile long*)0x40039058))
#define ADC1SSTSH0 (*((unsigned volatile long*)0x4003905C))
#define ADC1SSMUX1 (*((unsigned volatile long*)0x40039060))
#define ADC1SSCTL1 (*((unsigned volatile long*)0x40039064))
#define ADC1SSFIFO1 (*((unsigned volatile long*)0x40039068))
#define ADC1SSFSTAT1 (*((unsigned volatile long*)0x4003906C))
#define ADC1SSOP1 (*((unsigned volatile long*)0x40039070))
#define ADC1SSDC1 (*((unsigned volatile long*)0x40039074))
#define ADC1SSEMUX1 (*((unsigned volatile long*)0x40039078))
#define ADC1SSTSH1 (*((unsigned volatile long*)0x4003907C))
#define ADC1SSMUX2 (*((unsigned volatile long*)0x40039080))
#define ADC1SSCTL2 (*((unsigned volatile long*)0x40039084))
#define ADC1SSFIFO2 (*((unsigned volatile long*)0x40039088))
#define ADC1SSFSTAT2 (*((unsigned volatile long*)0x4003908C))
#define ADC1SSOP2 (*((unsigned volatile long*)0x40039090))
#define ADC1SSDC2 (*((unsigned volatile long*)0x40039094))
#define ADC1SSEMUX2 (*((unsigned volatile long*)0x40039098))
#define ADC1SSTSH2 (*((unsigned volatile long*)0x4003909C))
#define ADC1SSMUX3 (*((unsigned volatile long*)0x400390A0))
#define ADC1SSCTL3 (*((unsigned volatile long*)0x400390A4))
#define ADC1SSFIFO3 (*((unsigned volatile long*)0x400390A8))
#define ADC1SSFSTAT3 (*((unsigned volatile long*)0x400390AC))
#define ADC1SSOP3 (*((unsigned volatile long*)0x400390B0))
#define ADC1SSDC3 (*((unsigned volatile long*)0x400390B4))
#define ADC1SSEMUX3 (*((unsigned volatile long*)0x400390B8))
#define ADC1SSTSH3 (*((unsigned volatile long*)0x400390BC))
#define ADC1DCRIC (*((unsigned volatile long*)0x40039D00))
#define ADC1DCCTL0 (*((unsigned volatile long*)0x40039E00))
#define ADC1DCCTL1 (*((unsigned volatile long*)0x40039E04))
#define ADC1DCCTL2 (*((unsigned volatile long*)0x40039E08))
#define ADC1DCCTL3 (*((unsigned volatile long*)0x40039E0C))
#define ADC1DCCTL4 (*((unsigned volatile long*)0x40039E10))
#define ADC1DCCTL5 (*((unsigned volatile long*)0x40039E14))
#define ADC1DCCTL6 (*((unsigned volatile long*)0x40039E18))
#define ADC1DCCTL7 (*((unsigned volatile long*)0x40039E1C))
#define ADC1DCCMP0 (*((unsigned volatile long*)0x40039E40))
#define ADC1DCCMP1 (*((unsigned volatile long*)0x40039E44))
#define ADC1DCCMP2 (*((unsigned volatile long*)0x40039E48))
#define ADC1DCCMP3 (*((unsigned volatile long*)0x40039E4C))
#define ADC1DCCMP4 (*((unsigned volatile long*)0x40039E50))
#define ADC1DCCMP5 (*((unsigned volatile long*)0x40039E54))
#define ADC1DCCMP6 (*((unsigned volatile long*)0x40039E58))
#define ADC1DCCMP7 (*((unsigned volatile long*)0x40039E5C))
#define ADC1PP (*((unsigned volatile long*)0x40039FC0))
#define ADC1PC (*((unsigned volatile long*)0x40039FC4))
#define ADC1CC (*((unsigned volatile long*)0x40039FC8))

/////////////
#define NVIC_EN0_R (*((unsigned volatile long*)0xE000E100))//144

void UARTOutString(char *pt);
void UARTOutChar(char data);
void UARTInChar();
void UART_config();

unsigned int i;
unsigned char DATA[];

int main(void)
{
UART_config();

}

void UART_config()
{
RCGCUART |=0x00000001;
while((RCGCUART&0x01) == 0);
RCGCGPIO |=0X00001011;
AFSELA |=0x08;
DENA |=0x08;
AMSELE |=0x08;
UARTCTL &=~0x00000001;
UARTIBRD |=8;//115200 4=250000 1=1000000
UARTFBRD |=44;
UARTLCRH=(1<<5)|(1<<6);//disable FIFO & 8-bit data transmission
UARTCC &=0x00000000;//sys CLK
UARTCTL|=0x00000010;
UARTCTL|=0x00000001;
AFSELA |=0x03;
DENA |=0x03;
PCTLA |=0x00000011;
AMSELA &=0x00;
NVIC_EN0_R =(1<<5);//INT EN
UARTIM |=(1<<4);
UARTICR|=(1<<4);//clear RX INT
//UARTIFLS &=~0x3F;//CLEAR FIFO INT field PG-1186 UART Interrupt FIFO Level Select
//UARTIFLS &=0x00;//TX<=1/8 & RX>=1/8

}
void UART0_RXHandler(void)
{

i=UARTDR;
UARTICR|=(1<<4);
UARTOutString("{");
UARTOutChar(i);
UARTOutString("},");

}

void UARTOutString(char *pt){
while(*pt){
UARTOutChar(*pt);
pt++;
}
}
void UARTOutChar(char data)
{
while((UARTFR&0x00000020) != 0);
UARTDR = data;
}

void UARTInChar(void)
{
while((UARTFR&0x00000010) != 0);
i=UARTDR & 0x000000FF;

}

Arm-based microcontrollers

Arm-based microcontrollers forum

TM4C123GH6PM: UART Interrupts echoing incomplete data