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RTOS/TM4C1292NCPDT: Timer Interrupt Priority Versus HWI interrupt priority

Part Number: TM4C1292NCPDT

Tool/software: TI-RTOS

Hi,

I have created two Hwi ISR using .cfg file with default priority set i.e. -1 for GPIO(interrupt number 23) and SPI-DMA(interrupt number 46) and also i have created two timer ISR(timer 1 and Timer 3) using cfg file. Both timers are up counter and running periodically. dont have any option to set the timer priority in cfg file.

Now i want to understand how to set the priority for the timer ISR? I need reduce the priority of timer ISR than the HW ISR if its having higher priority than the HWI ISR. i dont have any issue if both timer and HWI ISR running with the same priority.

Regards

Bala

  • Hi,

    When you create a timer in BIOS, the Timer module automatically creates a Hwi instance for the timer interrupt.
    You should be able to change priority of this HWI instance.

    I would encourage you to go through section 8.3 of SPRUEX3T (www.ti.com/.../spruex3t.pdf)

    Hope this help.

    BR,
    Pranav.
  • Hi Pranav,

    Pranav Saraswala said:
    I would encourage you to go through section 8.3 of SPRUEX3T (www.ti.com/.../spruex3t.pdf)

    Weblink does not direct to correct web page. i have browsed and found the document in  weblink.  in the document does not described anything about priority settings for Timer ISR like HWI. 

    and also i referred the Timer_Params definition and not found priority parameter definition.

    i have checked my HWI detailed in ROV. where i can found all the HWIs(HWI, Timers, EMAC and WDT) are set to 224 priority number and priority group is 7. does these running in high priority?

    Regards

    Bala

  • Hi,

    Please find my ROV of HWI detailed view.

    There are some unknown HWI is generated(Highlighted) with High priority than other HWI. How can get information about those interrupts? if its CPU specific, will they run in periodic or during boot up?

    Reagrds

    Bala

  • Hi Bala,
    I think this post has the answer to your question about changing the timer priority.
    e2e.ti.com/.../566475
  • Rather than doing that much of jugglery, wouldn't it be easier to configure timer using Tiwavare API calls ?

    There must be some easier means of accessing priority of bios timer hwi !
  • Yes, you can use the TivaWare to configure (i.e. setting up the period) the timer but let the Hwi to manage the timer's interrupt.
  • Hello Charles,

    i have looked at the way of setting the priority for timer HWI and it works well. As Pranav said, there should be an easiest way to set the priority of the time HWI.

    i have another clarifications. As design indent, my application is performing the I2C read in HWI context using Tivaware I2C library calls and HWI have been set with default priority of TI RTOS. as far as my ROV says it has priority of 224 and group priority of 7.

    is there any other RTOS used HWI will interrupt my I2C read transactions? do i need to take care anything when we use tivaware library inside HWI context? because if its breaking in mid of I2C transaction, I2C bus error will occurs and leads to power cycle the device to bring the normal operations.

    Regards
    Bala
  • Hi Bala,

     If you look at the datasheet the I2C0 has the interrupt vector number of 24. This means any peripheral or exception of higher priority will preempt the I2C.

      Please refer to the NVIC section in the datasheet to change the group priority for I2C if you want the I2C to higher group priority than others. For example, you can change I2C to take group priority of 0 instead of 7 which will give I2C higher priority over other peripherals. 

  • Hello Charles,

    Please look at the snapshot which i posted into the forum on Jun 18, 2018 11:44 AM regarding my HWI detailed view. Here i believe all the ISR has been assigned with TI RTOS default priority(224) and priority group(7). Since all ISR is assigned with same priority and priority group, One ISR will nit interrupt other ISR. Am i right?

    Regards
    Bala
  • Hi Bala,

    First of all the NIVC (Nested Interrupt Vector Controller) as implemented in the TM4C can only support 8 priority levels since only three bits are implemented for each interrupt request. Looks like the TI-RTOS is configuring all interrupt requests to priority level 7. Note that priority level 0 will have higher priority than priority level 1,2,3...,7.

    With all that said, if all interrupt requests are configured to the same priority level of 7 then if multiple interrupts are pending at the same time, the interrupt with the lowest IRQ number is processed first.

    If you refer to the table I showed in my last reply, if GPIOA becomes pending in the middle of I2C0 iISR then the GPIOA will preempt I2C0 given that both are configured the same priority. This is what I said if you want I2C0 to have higher priority than GPIOA then you will need to change the priority level for I2C0. For example, you can change the priority level for I2C0 to level 0 or even level 6 will have higher priority than level 7.

    Please refer to the sub-section 'Exception Priorities' and 'Interrupt Priority Grouping' in the The Cortex-M4F Processor chapter in the datasheet for details on the priority handling. To change the priority you will need to configure the PRIx registers in the NVIC module.
  • Hi Charles,

    Thank you for the detailed response which is really helpful.

    Charles Tsai said:
    To change the priority you will need to configure the PRIx registers in the NVIC module.

    will it making changes to PRIx registers in the NVIC module, if we change the priority of the HWI ISR in cfg file? or do we need to use separate API call to set this register?

    Regards

    Bala

  • Hello Charles,

    i have looked at the datasheet which you pointed out and found contradictory to your statement.

    Charles Tsai said:
    If you refer to the table I showed in my last reply, if GPIOA becomes pending in the middle of I2C0 iISR then the GPIOA will preempt I2C0 given that both are configured the same priority.

    but datasheet says

    Can you please clarify?

    and also what is API should i use to change the priority group in TI RTOS?

    Regards

    Bala

  • Hi Bala,
    Thanks for quoting the statement in the datasheet. You are correct about the preemption handling such that an interrupt already being handled will not be preempted by another interrupt of the same priority even with lower exception number. However, bear in mind it is still true that If two interrupts are of same priority and are pending at the same time then the interrupt with the lower exception number will have priority to be service first.

    To change the priority use IntPrioritySet() API.
  • Hello Charles,

    Thank you for the clarifications.

    i am facing an serious issue in my application which i am not able to get it closer.

    Please look at the snapshot which i posted into the forum on Jun 18, 2018 11:44 AM regarding my HWI detailed view. here i have created only two HWI belongs to interrupt number 23 and 46. i believe rest of the HWIs are generated from RTOS based on interface used in my applications task( for I2C, SPI, EMAC etc peripheral drivers). somehow my ISR belongs to 46 is preempted by other higher priority task leave I2C bus fault. how do i find which ISR is preempted HWI 46?

    and also i have tried changing the priority to higher for HWI 46. but its failed in some other HWI used by RTOS.

    do you have any suggestions?

    Regards
    Bala
  • Hi Bala,

     46 is the GPIOF. Are you generating an GPIOF interrupt based on an edge detection from an external input? If yes, how fast is the input? Can you elaborate?

     What is the 23? The 23 is supposed to be the SSI0 according to the datasheet. But in your ROV it is showing ADC. I'm confused here.  

     Which I2C is creating bus fault? When you said bus fault do you mean bus fault as in vector number 5 shown below?

     I don't think the 46 is preempted by others since you said all interrupts have the same priority. As we just went through the priority handling discussion, if two interrupts (i.e. 46 and 23) are of same priority and if both are pending at the same time then the lower exception number interrupt (i.e. 23) will take priority to be serviced. This is different from 46 is being preempted in the middle of the interrupt handling.

  • Hello Charles,

    Charles Tsai said:
     46 is the GPIOF. Are you generating an GPIOF interrupt based on an edge detection from an external input? If yes, how fast is the input? Can you elaborate?

    This is configured as level triggered. the interrupt frequency would be in microsecond interval.

    Charles Tsai said:
    What is the 23? The 23 is supposed to be the SSI0 according to the datasheet. But in your ROV it is showing ADC. I'm confused here

    This SSI0 DMA interrupt will be used for External ADC.

    Charles Tsai said:
     Which I2C is creating bus fault? When you said bus fault do you mean bus fault as in vector number 5 shown below?

    i meant, the i2c bus transaction breaking at middle of transfer.

    Charles Tsai said:
     I don't think the 46 is preempted by others since you said all interrupts have the same priority. As we just went through the priority handling discussion, if two interrupts (i.e. 46 and 23) are of same priority and if both are pending at the same time then the lower exception number interrupt (i.e. 23) will take priority to be serviced. This is different from 46 is being preempted in the middle of the interrupt handling.

    Yes as per the datasheet, it should not be preempted. Is there any possibility that TI RTOS used hardware resource is generating an interrupt which may be configured in higher priority group?

    Regards

    Bala

  • Hi Bala,
    Not sure if you are making some progress here. Have you tried to manually make I2C higher priority than all others?
    Also, what is the reason you are not making GPIOF edge-trigger but level-trigger?
  • Hello Charles,

    Yes. through my testing, found no HWI preemption i happening when we set all are with same priority. its some other issue which we are debugging now.

    Charles Tsai said:
    what is the reason you are not making GPIOF edge-trigger but level-trigger?

    Its external device design intend to configure it in level trigger. please refer the more about this conversation in following thread.

    Regards

    Bala