This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8350F: Clarification on ENABLE/VDRAIN behavior

Part Number: DRV8350F

Hello,

In our design, we have a 28V power on VDRAIN and a 15V power on VM.
The 15V power is always there but the 28V power can dissapear.

We did that in order to keep the driver configuration even in case of 28V power loss, which is a nice addition to the component compared to previous generations.

However, from my understanding of the datasheet, it seems that even for the configuration of the component, the ENABLE pin must be activated (despite being flagged as GATE driver enable).
Do you confirm ?

Does the VDRAIN power need to be present too in order to configure the component ?

In case of loss of the VRAIN power, do you confirm the configuration is kept ?

In case of deactivation of the ENABLE, do you confirm the configuration is kept ?

Best regards,
Clément

  • Hi Clément,

    The ENABLE pin must be pulled high with 3.3V (max of 5.75V) to enable the gate drivers. The ENABLE pin has a internal pull down resistor, meaning if you don't apply an external voltage to this pin, the gate drivers will be disabled. 

    If at any time the input supply voltage on the VM pin falls below the VVM_UV threshold or voltage on VDRAIN pin falls below the V VDR_UV, all of the external MOSFETs are disabled, the charge pump is disabled, and the nFAULT pin is driven low. The FAULT and UVLO bits are also latched high in the registers on SPI devices. Normal operation continues (gate driver operation and the nFAULT pin is released) when the under voltage condition is removed. The UVLO bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST, an 8 to 40-µs pulse can be used to reset fault conditions).

    See section 8.3.6 for more details relating to gate driver protection circuits. 

    Let me know if you have any more questions.

    Thanks,

    Michael

  • Hi Clément,

    I wanted to note that ENABLE is required for SPI,  so if ENABLE is deactivated then you'll lose your SPI configuration.

    I'm setting up this experiment in the lab to see the loss of VDRAIN will keep the SPI configurations, I will get you the results ASAP.

    Thanks for your patience,

    Michael

  • Hi Clément,

    From my tests VM goes in UVLO the DVDD voltage will go low and you will not have SPI communication.

    If VDRAIN goes into UVLO and VM is still properly powered, DVDD will remain high and there is no reset of SPI, the registers will not be reset. 

    As stated in the post above: ENABLE is required for SPI,  so if ENABLE is deactivated then you'll lose your SPI configuration.

    Thanks,

    Michael

  • Hi Michael,

    I wanted to note that ENABLE is required for SPI,  so if ENABLE is deactivated then you'll lose your SPI configuration.

    Thank you for your answer, this was the bit I was seeking info on.

    Clément

  • Hi Clément,

    Thanks for your confirmation. Please let us know if you have any other questions!

    Thanks,

    Matt