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DRV8353F: Current sense differences with DRV8323RS?

Part Number: DRV8353F
Other Parts Discussed in Thread: DRV8353, DRV8323

Hi, I had a functional design based on the DRV8323RS and have redesigned it around the DRV8353F to work around shortages (I know common story).  The problem I am having is unusual noise on the current sense lines.  In this design, the schematic and layout are pretty much the same between the two versions, aside from an external regulator instead of the built-in that was used on the DRV8323RS version.  In the DRV8353F design though, each of the current sense channels has a board specific and channel specific noise that is both large, and hard to describe.

For some reason, channel C always appears to be relatively noise free, but channels A and B sometimes, but not for every board, have varying amounts of noise measured on the current sense outputs.  The driver is configured in 3x mode, with the CSA gain configured to 20.  Current sense ADC sampling is conducted at the center of the off time.  For the good channel C (and the previous board), with a 50% duty cycle on all channels, I measure a standard deviation of around 1.3 mV (around 1-2LSB on the 12 bit ADC of the microcontroller).  On the bad channels of the DRV8353F board there is often a background noise of around 4 mV, with aperiodic spikes up to 80 mV.

I believe the external regulator in the new design is relatively well laid out.  There are separate ground planes for the power and logic/sense regions connected under the regulator (and at the AGND pin of the DRV8353).  Neither the current sense inputs nor outputs run near anything that is switching during the sampling time and I don't see any significant power supply related noise with the oscilloscope, and in any case, one channel works just fine, which would seem to rule out power supply noise.

Under a microscope, all the solder joints look fine on all components.  

Are there notable differences between the current sense amplifiers on the two chips that I should be aware of?

My layout for the FETs and current sense resistors looks like:

And the current sense outputs run to the microcontroller like so:

I don't have the best probing setup, so attaching the scope probes does couple some additional noise into the system.  Specifically, when I probe the debug line that signals ADC sample, it shows up as extra noise on the current sense output that is not actually a problem.  So first, a scope trace of a "good" channel C.  In this plot, yellow is the "SOC" line, AC coupled, teal is a debug line indicating the end of the ADC sample (which starts just a microsecond or so before that line goes high), and purple is the INHA line (all 3 channels are the same).

 

Followed by a closeup of the sampling window, and a second close-up with the debug probe removed, as it was coupling a moderate amount of noise into the scope reading:

That sag in the line is clearly related to the sampling, and may just be a ground level issue in my probing as the microcontroller draws more current when running the ADCs?  This being the "good" channel, I don't see that level of noise in the readings for sure.

Now, for one of the "bad" channels in two variants.  Sometimes it has terrible noise for the entire time the gate drive is low, sometimes only partway through.

Now, a close-up of that:

It is almost as if the sense amplifier is becoming unstable for some reason.

However, even for channels without that noise which is obviously bad on the scope, the "sag" associated with sampling is more variable, larger, and results in increased measured noise.

Finally for reference, scope traces taken in the same way from the DRV8323 based design, which for all channels resembles the channel C output from the DRV8353F

  • And I forgot to state that the super noise from channel A can be observed on the sense resistor input although there is nothing different in the schematic or significantly different in the layout between channels.

    Channel A sense resistor:

    Channel C sense resistor:

  • Hi Josh,

    That noise has frequency of about 13MHz, well above switching frequency of DC/DC converters. I would look for anything in the circuit that works/rings at that frequency. First I would check all Mosfet gate voltages and switching node voltages. There was recently case with another DRV where HS gates rang terribly at around 4.2MHz.

    https://e2e.ti.com/support/motor-drivers-group/motor-drivers/f/motor-drivers-forum/998606/drv8301-ringing-on-high-side-vgs-at-turn-on-may-be-casuing-vds-over-current

    To look for the source of such frequencies close field probe may be handy.

    Regards,

    Grzegorz

  • Yeah, the 1x MHz is confusing.  The regulator is at 500kHz, you can clearly see its ticks even in the clean signal.

    All the switching nodes seem perfectly clean.  Here are scope traces from the channel A low side gate, high side gate, and switching node (in teal, with yellow still being current sense output and magenta being INHA):

    All three channels look equally as clean. 

    Certainly there is nothing in the circuit that is intentionally operating at that frequency.  I will try and get a close field probe to see if I can find something else, but there isn't a whole lot else to this circuit.

  • Hi Josh,

    Thanks for posting on the MD forum. I appreciate how detailed the question is + all the waveform pictures.  

    I will review the data you sent over tomorrow with other members in my group, and I'll get you some resolution on the noise issue you're having on SOx.

    Also, thank you to Grzegorz for your input.

    Regards,

    Michael

  • Hi Josh,

    Thanks for sharing the waveforms. All waveforms look clean except those current sense signals. I have just a few more thoughts. The difference I could notice between channels A/B and C is that channels A and B share the same ground point for their sense resistors. Noise on sense resistor on channel A seems to be present all the time during switching INHA input. 

    For noise measurements on SOX outputs and on sense resistor did you use power ground or AGND as a reference?

    If you could make measurements of signals on SOX outputs and on sense resistors but with DC coupling to check if voltages are within limits for amplifiers.

    If you could also make measurements of voltages between ground side of sense resistors and VREF against AGND?

    Regards,

    Grzegorz

  • For noise measurements on SOX and the sense resistor both I used AGND as a reference.  I realize for the sense resistor I should have used power ground, but the noise was obviously different between the three channels relative to AGND so didn't figure it made a difference.

    Here is a plot of SOB w/ DC coupling:

    And for the sense resistors against AGND:

    As mentioned, my probing setup isn't great, so I'm not sure if those transients are real, but it is centered around 0V.

    Here is a plot with yellow being AC coupled between AGND and the ground of the channel B sense resistor, and teal is SOB, also AC coupled:

    So there is a moderate amount of maybe noise on the sense resistor ground, but it doesn't seem necessarily related to when the noise appears on SOB (as in this plot the noise on SOB stops halfway through around when the ADC samples, but the noise on the ground node doesn't really change).

    Here is VREF measured against AGND first AC coupled:

    And then DC coupled:

    I will say that it may be something to do with the ground plane layout surrounding the channel A and B sense resistors, as that did get tweaked slightly to add more clearance between the power and ground planes for a higher voltage rating.

    The old (working) version:

    And the new (non-working) version:

    It may be that the old version was just marginal and the new ground layout tweaked it too much into instability?  I noticed that SLVA959A (which was published after this design was originally drawn), recommends a 1nF decoupling cap between SPX/SNX.  Is that just for noise performance generally, or to prevent instabilities like this?

  • Hi Josh,

    Thanks for all waveforms again.

    Re waveform 1. SOB voltage = 1.68V, close to the middle of 0.25-3.0V, some small noise present when problem occurs - OK

    Re 2. voltage on sense resistor stays well (except switching noise) within +/- 0.3V - OK

    Re 3. there is not much noise between grounds, there is some noise around 650kHz on SOB, probably from some DC/DC converter. I can not say if it has any influence on the problematic noise.

    Re 4&5. VREF = 3.24V, it is within 3.0 - 5.5V limits and some noise is present, MLCC cap close to VREF and AGND pins plus ferrite bead may help but again it is hardly to say if that noise plays any role.

    Capacitor 100pF-1nF between SPX and SNX pins close to driver IC increases immunity against strong EMI and probably filters out switching noise. Capacitor around 10nF parallel to sense resistor may lower its parasitic inductance and make switching noise in half-bridge smaller - that I need to verify yet. I do not know if these capacitors would have any influence on circuit stability.

    Again everything looks fine (just my opinion) except that noise in CSA circuit, I do not know what can cause noise of such frequency and sustain it for a while. Any changes to the circuit like some extra caps may change the situation and bring some answers. Some simple solution might be RC filter between SOX outputs and ADC inputs, noise frequency is high enough to use such filters. It would probably solve ADC error problem but the source of noise would likely remain.

    Regards,

    Grzegorz

  • Hi Josh again,

    Just something crossed my mind. Motor cable might have enough inductance and capacitance to resonate at 1xMHz. The noise occurs on sense resistor, its grounded end is quite clean, impedance of sense resistor is quite low while input impedance of  SPX input probably is quite high and there is little chance that noise comes from DRV8353 to sense resistor. The noise occurs while INHA input is low so LS Mosfet is on and sense resistor is connected to motor cable. If you could shorten motor cable or replace it with another type and check if it changes anything. It is just another my theory, I have never experienced problems with motor cable resonances, not yet.

    Regards,

    Grzegorz

  • Hi,

    This will take an additional day to look over. 

    Sincere apologies for the delay.

    Thanks,

    Michael

  • Hi,

    SPA/SNA and SPB/SNB are not routed differentially, so there is a higher probably there will be noise or reflections on these phases.  There are also right angles SPA and SPB, which is not ideal.

    The vias that you’re using to connect ground are very large and we recommend using multiple smaller vias. We recommend splitting the grounds for SNA and SNB (v- on your layout). This is because the ground noise caused by the added inductance of the large vias can couple over to SNA and SNB.

    To address you question of are there notable differences between the CSA on the two chips? They are identical. To your other question, the cap between SPx and SNx is for CSA input filtering.

    We have a document that goes over Best Practices for Board Layout of Motor Driver, I recommend you look over the CSA section.

    https://www.ti.com/lit/an/slva959a/slva959a.pdf

    Thanks

    Michael

  • Thank you for the recommendations! 

    I'm not 100% sure I understand your suggestion to split the grounds for SNA/SNB.  Do you just mean tie them into the ground plane (V- in my layouts above) at different places using different sets of vias?  Or do you mean create a separate ground plane under them leading up to the chip.  If the latter, is there a recommended way to terminate that ground plane peninsula?

  • Would you be willing to take a quick look at this layout and see if it more closely adheres to the recommended guidelines or if there any other obvious problems?  More smaller vias are used, the SNA and SNB sense resistors are tied to ground separately, and the sense Kelvin signals are routed differentially.

  • Hi Josh,

    This layout appears a lot tighter and better, since the CSA inputs are routed differentially and use Kelvin connections now. Previously, because SPB/SNB was routed differentially, and SNA/SNB shared the ground plane on the top layer, it was more likely for mV of noise generated from SPB/SNB to couple into SPA/SNA. 

    Even though SNA and SNB are still connected to V- on a presumed common GND place, by ensuring on the top layer that these "grounds" are split into their own regions (with lots of small vias for sinking current), you are ensuring that mV of noise will not couple between each phases' CSA inputs. The only coupling that is okay to see in CSA inputs should be similar noise coupled between SPx/SNx - which by routing differentially - should cancel the differential noise since its a differential input to the CSA itself.

    Essentially, the differential routing should reduce noise that may have been previously introduced on SPB/SNB, and the separation of V- on the top plane for SNA and SNB should reduce any coupling of noise from SNB to SNA. 

    Hopefully this explains more. 

    Thanks,
    Aaron

  • Aaron,

    I will spin something like that and see how it works.

    Regards,
    Josh

  • Hi Josh,

    Is there any additional help needed on this thread?

    Thanks,

    Matt

  • Well, I was waiting for a respin to be manufactured to see if these suggestions resolved the issue.  If you like, I can accept the previous solution (since I did take the advice, just don't know if it works), and open up a new thread if I continue to have problems?

  • Hi Josh,

    Sure! You can click the "Ask a related question" button to open a new thread.

    Thanks,

    Matt