due to the switching edges of the FET's there is a ground rise between AGND and GND.
Measured with the oscilloscope there are voltages of 2V peak-to-peak between GND and AGND.
In my opinion, this circumstance leads to the fact that the input signals are not correctly detected.
We have already placed a 1nF and a 150nF capacitor between VDD and AGND.
Do you have any recommendations how to minimize this influence?