DRV3245Q-Q1: VGS error detection

Martin Steube-Henkel

Part Number: DRV3245Q-Q1

Hey Adam

Hella have an urgent follow up regarding the VGS monitor in general.

According to the datasheet the VGS error detection threshold High-level for PVDD_UVFL = 1 (undervoltage warning flag) is set to 1.2 to 2.3V (which is in huge parts even lower than the Low-level threshold).

Can you please check if this information is correct or if the given thresholds apply for an undervoltage fault instead.

If the given information is correct it would essentially mean that in the worst-case we already loose half of the VGS detection for PVDD < 8.35V, and we cannot fulfill the safety concept below this voltage.

In that case would see the urgent need of an alignment meeting.

over 2 years ago

0 Adam Sidelsky over 2 years ago

TI__Guru 61360 points

Martin,

Please schedule a short meeting with myself and Toshio and we can explain this.

Regards,

-Adam

0 Martin Steube-Henkel over 2 years ago in reply to Adam Sidelsky

TI__Intellectual 1250 points

As discussed during our call yesterday please find the description to explain warning flag is cleared by SPI read command.

Accordingly to the

But this is confusing because in the table is nothing written that UV warning can control the nFault. The table is related to the SPI flag only

Why regarding DeadTime violation the (2) is only linked to the PL (enforece(2)) è does this means, the disabling of the gate driver is only working if WARN_MODE=1 and the nFAULT pin is comes always -> or is this related to the nFAult pin