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DRV3255-Q1: Gate drive current control with IDRIVE

Part Number: DRV3255-Q1

My customer would like clarification on the following: Is the gate drive current controlled or do the different IDRIVE settings just change the source/sink resistance? It's a little unclear because of the inclusion of both current and resistance specs and the feature description doesn’t have much detail in the preliminary datasheet.

I think the gate driver current is controlled by the different IDRIVE settings, but the source pullup / sink pulldown resistances are slightly different due to RDSon characteristics of the different predriver MOSFETs needed for the different gate drive current settings (as shown in Figure 2-1 of this app note: https://www.ti.com/lit/an/slva714d/slva714d.pdf).

Thanks.
Alan

  • Hello Alan,

    Thanks for posting to the MD forum, I will get back to you with a response shortly!

    Best,

    Isaac

  • Hi Isaac, any update?

  • Hello Alan,

    Sorry of the delay on the response.

    The reason there are both current and resistance specs are given is due to the different operating regions of a MOSFET. The current spec represents the behavior of the internal transistor while it is operating in the saturation region, and the resistance spec will represent the behavior of the transistor in the linear region.     

                                    

    When the internal pullup/pulldown FET first turns on, there is a large VDS (voltage difference between BSTx-GHx, GHx-SHx, VGLx-GLx, or GLx-SLx) across the internal transistors. Effectively putting the FET in the saturation region, which means the device will be providing its "peak" pullup or pulldown current. Which are the current values you will see in the spec for the peak source pullup (or sink pulldown) current.

    When the external MOSFET is charged or discharged, the VDS of the internal transistor will decrease, and it will eventually enter the linear region of operation. The transistor begins to act like a resistor, which is why this resistance spec is provided. 

    The device has the following architecture (Figure 2-2 of the app note referenced above):

                                

    The resistance values vary slightly due to the difference in the supply architecture for HS and LS transistors (HS is bootstrap + trickle charge pump, and LS is supplied from VGLx).

    I hope this clears up some of the confusion!

    Best,

    Isaac

  • Thanks for the detailed response Isaac. I'll let you know if any other questions arise.

  • Thanks Alan!