• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 29 subscribers
  • Views 139 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRV8830: Drive status during a stall condition

Alin Paun
Prodigy 10 points
Part Number: DRV8830

Hello,

In the datasheet of the IC in question (DRV8830) we have section 7.3.3, specifically bellow quoted paragraph which describes the driver behaviour during a stall event.

If the current limit condition persists for some time, it is likely that a fault condition has been encountered, such as the motor being run into a stop or a stalled condition. An overcurrent event must persist for approximately 275 ms before the fault is registered. After approximately 275 ms, a fault signaled to the host by driving the FAULTn signal low and setting the FAULT and ILIMIT bits in the serial interface register. Operation of the motor driver will continue

It is unclear to me though if the driver remains functional, thus pumping current into the DC motor, after the stall event is detected.
The last afirmation "Operation of the motor driver will continue."  seems to indicate so, but does it refer to the driving stage (H-bridge) being automatically switched-off after stalling detection occurs?

  • +1
    TI__Mastermind 37683 points

    Hi Alin,

    Sorry for the confusion on the datasheet. The table below shows the H-bridge and internal circuits status in response to various faults. In the case of OCP, the H-bridge will be disabled but the device internal circuits will be functional. The H-bridge will remain disabled until the device is reset by power cycle of VCC.

  • 0 in reply to Pablo Armet
    Prodigy 10 points

    Thanks for the prompt and quick answer.

    A new questions comes to my mind then: considering an OCP flag occurs at t0 = 275ms (according to the datasheet an OC event needs to persist for 275ms before being detected) what would be the time offset in respect to t0, be it t_H_disabled, at which the H bridge gets dissabled?  

  • +1 in reply to Alin Paun
    TI__Mastermind 37683 points

    Hi Alin,

    After the fault occurs, there will a propagation delay from when the driver gives the command to disable the FETs and when the FETs actually are disabled. This propagation delay is not given in the datasheet but it is in the range of  nano seconds (~100-300ns). I hope this answers your questions