DRV8305-Q1: with a brushed motor

Hi Kura-san,

Yes you can use a single phase brushed DC motor. Connect other end to PVDD or GND for unidirectional control with HS or LS driver. 

Please short SHC and SLC to GND, and float GHC and GLC. This will ensure VDS_OCP is never triggered since VDS = 0V and VGS = 0V, as long as you don't turn on phase C's INHC/INLC signals. 

Thanks,
Aaron

Hi Kura-san, 

This diagram looks good, you should connect to PG1 because shunt resistor can trigger voltage potential that couples into the SLx trace, which could trigger overcurrent if monitoring with respect to PG2. Connect SLC = SHC = PG1. INLC and INHC look good too. Ensure SG, PG1, and PG2 have minimal voltage potential difference between split grounds. 

Thanks,
Aaron

Hi Kura-san, 

1) I think these ranges exists due to the CSA gain settings, with the min setting = 10V/V. If common input exceeds +/-0.15V, then if VREF = 3.3V and G = 10, then Vo = +/-1.5V and this would be at the limits of the linear range of the SOx output. I think you may be able to marginally exceed +/- 0.15V if VREF is 5.0V rather than 3.3V. I need to confirm why this spec is written this way.

2) For current detection in the pre-driver, are you referring to VDS_OCP or SNS_OCP? Is Rp1 or Rp2 the shunt resistor?

For VDS_OCP, the equation for overcurrent to trigger is I_DS * Rds_on > VDS_OCP
For SNS_OCP, the equation for overcurrent to trigger is 2V > SL_x - GND, where SL_x - GND = I_shunt * R_shunt. 

This also assumes that the layout is good enough so there isnt a ground potential difference to cause noise at SL_x or GND, and ensuring that if there is ground potential difference, the durations of the noise are shorter than OCP deglitch times. 

3) For a Brushed_DC motor, you should have control over each half bridge. This means you should use 6x PWM mode or 3x PWM mode (setting 00b, 01b, or 11b). 

Thanks,
Aaron

Hi Kura-san,

Sorry for the delay in reply. 

1) VIN_COM is the offset from SPx/SNx to GND seen by both inputs, and which should not be visible in the SOx output. The common mode input range is how much common mode can be applied to SPx/SNx while operating within spec. For example, if you tie SNx/SPx together, the output should be at VREF/k, and then if you vary the offset of SNx/SPx to GND, you shouldn’t see SOx move as long as you stay within the common mode spec. VIN_COM is valid for all gain settings, unrelated to the output voltage or VREF division setting. However, the actual circuit limitation is due to a body diode path between SPx/SNx to SOx, so it can be exceeded in certain situations. 

2) For the wiring resistors for harnesses, I would ensure that the resistance difference between PG and SG is negligable in that there is not there is not a voltage potential difference that causes incorrect current measurements. 

For instance, if Rp1 = Rp2 = 1 ohm, then there will be Rp_eq = 0.5ohm resistance between signal GND and SG/PG. If signal GND goes to MCU, and SG/PG sees 50mV (i.e. V_Rp = I_motor * Rp_eq), then then the SOx calculation will be 50mV inaccurate to calculate current feedback. You would also need to ensure added inductance is not introduced from the wiring harness, or else this may cause voltage spiking when motor current is switching. 

Thanks,
Aaron

Hi Kura-san,

The information about the body diode and diagram is shown in the snippet below.



Thanks,
Aaron